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公开(公告)号：US11474821B1
公开(公告)日：2022-10-18
申请号：US17318252
申请日：2021-05-12
发明人： Amir Turi , Avraham Ayzenfeld , Gilad Shimon Merran , Yanai Danan , Amit Shay , Yossi Shapira , Yair Fried , Oren Ben Gigi , Omri Rafaeli
IPC分类号： G06F9/38
摘要： In an approach to processor dependency-aware instruction execution, responsive to a new instruction being issued to an instruction issue queue in a processor, a future dependency count is incremented for each instruction of a plurality of instructions in the instruction issue queue that has a dependency on the new instruction. The plurality of instructions in the instruction issue queue are prioritized based on the future dependency count. The highest priority instruction of the plurality of instructions in the instruction issue queue is issued.
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公开(公告)号：US11074184B2
公开(公告)日：2021-07-27
申请号：US16383705
申请日：2019-04-15
发明人： Michael Cadigan, Jr. , Erez Barak , Deepankar Bhattacharjee , Yair Fried , Jonathan Hsieh , Martin Recktenwald , Aditya Nitin Puranik
IPC分类号： G06F12/0815
摘要： Methods, systems and computer program products for monitoring delivered packages are provided. Aspects include receiving, by a co-processor, a data stream and performing processing on the data stream. Aspects also include writing, by the co-processor, a data record into the output buffer. Based on a determination that the data record should replace a most recently stored data record in a cache, aspects include providing, by the co-processor to the cache controller, an instruction for the cache controller to write the data record to a location in the cache obtained from a most recently used address register. Based on a determination that the data record should not replace the most recently stored data record in the cache, aspects include writing, by the cache controller, the data record to an available location in the cache.
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公开(公告)号：US11144321B2
公开(公告)日：2021-10-12
申请号：US16280285
申请日：2019-02-20
摘要： Examples of techniques for store hit multiple load side register for operand store compare are described herein. An aspect includes, based on detecting a store hit multiple load condition in the processor, updating a register of the processor to hold information corresponding to a first store instruction that triggered the detected store hit multiple load condition. Another aspect includes, based on issuing a second store instruction in the processor, determining whether the second store instruction corresponds to the information in the register. Another aspect includes, based on determining that the second store instruction corresponds to the information in the register, tagging the second store instruction with an operand store compare mark.
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公开(公告)号：US10929142B2
公开(公告)日：2021-02-23
申请号：US16358791
申请日：2019-03-20
发明人： Gregory William Alexander , James Bonanno , Adam Collura , James Raymond Cuffney , Yair Fried , Jonathan Hsieh , Jang-Soo Lee , Edward Malley , Anthony Saporito , Eyal Naor
摘要： Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.
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公开(公告)号：US10977040B2
公开(公告)日：2021-04-13
申请号：US16279052
申请日：2019-02-19
发明人： James Raymond Cuffney , Adam Collura , James Bonanno , Jang-Soo Lee , Eyal Naor , Yair Fried , Brian Robert Prasky
摘要： Methods, systems and computer program products for heuristically invalidating non-useful entries in an array are provided. Aspects include receiving an instruction that is associated with an operand store compare (OSC) prediction for at least one of a store function and a load function. The OSC prediction is stored in an entry of an OSC history table (OHT). Aspects also include executing the instruction. Responsive to determining, based on the execution of the instruction, that data forwarding did not occur, aspects include incrementing a useless OSC prediction counter. Responsive to determining that the useless OSC prediction counter is equal to a predetermined value, aspects also include invalidating the entry of the OHT associated with the instruction.
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公开(公告)号：US10649777B2
公开(公告)日：2020-05-12
申请号：US15978245
申请日：2018-05-14
发明人： Yossi Shapira , Eyal Naor , Gregory Miaskovsky , Yair Fried
IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30
摘要： Prefetching data by determining that a first set of instructions that is processed by a computer processor indicates that a second set of instructions includes multiple iteration groups, where each of the iteration groups includes one or more loop-unrolled instructions, monitoring the second set of instructions as the second set of instructions is processed by the computer processor after the first set of instructions is processed by the computer processor, mapping a corresponding one of the loop-unrolled instructions in each of the iteration groups of the second set of instructions to a stride-tracking record that is shared by the corresponding loop-unrolled instructions, and prefetching data into a cache memory of the computer processor based on the stride-tracking record.
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公开(公告)号：US20230315631A1
公开(公告)日：2023-10-05
申请号：US17709807
申请日：2022-03-31
发明人： Yair Fried , Aaron Tsai , Eyal Naor , Christian Jacobi , Timothy Bronson , Chung-Lung K. Shum
IPC分类号： G06F12/0811
CPC分类号： G06F12/0811 , G06F2212/311
摘要： Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.
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公开(公告)号：US11157281B2
公开(公告)日：2021-10-26
申请号：US15988070
申请日：2018-05-24
发明人： Eyal Naor , Yossi Shapira , Yair Fried , Amir Turi
IPC分类号： G06F9/345 , G06F12/0862
摘要： Prefetching data by detecting a predefined pattern of register activity of a computer processor by detecting when data, at a memory address pointed to by the sum of an offset value and the contents of a register of the processor during an instruction cycle of the processor, is loaded into the register as a result of processing an instruction, detecting the pattern by detecting when data, at a memory address pointed to by the sum of the offset value and the contents of the register during at least one subsequent instruction cycle, is loaded into the register as a result of again processing the instruction, and prefetching data, into a cache memory of the processor, from a current prefetching memory address, where data, at a memory address pointed to by the sum of the offset value and the contents of the register, is used as the current prefetching memory address.
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公开(公告)号：US20200264885A1
公开(公告)日：2020-08-20
申请号：US16280285
申请日：2019-02-20
摘要： Examples of techniques for store hit multiple load side register for operand store compare are described herein. An aspect includes, based on detecting a store hit multiple load condition in the processor, updating a register of the processor to hold information corresponding to a first store instruction that triggered the detected store hit multiple load condition. Another aspect includes, based on issuing a second store instruction in the processor, determining whether the second store instruction corresponds to the information in the register. Another aspect includes, based on determining that the second store instruction corresponds to the information in the register, tagging the second store instruction with an operand store compare mark.
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公开(公告)号：US10572387B2
公开(公告)日：2020-02-25
申请号：US15867989
申请日：2018-01-11
发明人： Dwifuzi Coe , Yair Fried , Martin Recktenwald , Yossi Shapira
IPC分类号： G06F12/0891 , G06F12/0831 , G06F12/128
摘要： A memory access control includes a tracker configured to receive cache invalidate (XI) commands from the memory controller and to provide responses to the memory controller and an address storage element in the tracker that stores an address to be locked by one of the processing units. The system also includes a lock required, a cache invalidate (XI) tracker bit, a set input that upon receipt of a set command sets the lock required bit when a first condition is met, a first reset input that resets the lock required bit upon receipt of a reset command; and a second reset input that resets the XI tracker bit. The tracker rejects incoming XI commands from the memory controller when the lock required bit is set, allows incoming XI commands when the lock bit is not set and sets the XI tracker bit when a first incoming XI command is received.
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