公开(公告)号：US20180114849A1

公开(公告)日：2018-04-26

申请号：US15838456

申请日：2017-12-12

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7827

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

公开(公告)号：US20180069024A1

公开(公告)日：2018-03-08

申请号：US15795454

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Zuoguang LIU ,  Xin MIAO

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76281 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66583 ,  H01L29/7838 ,  H01L29/7842 ,  H01L29/78684

Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

公开(公告)号：US20170352743A1

公开(公告)日：2017-12-07

申请号：US15617573

申请日：2017-06-08

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/3065 ,  H01L29/417 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/02609 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7827

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

公开(公告)号：US20190318963A1

公开(公告)日：2019-10-17

申请号：US15951355

申请日：2018-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin MIAO ,  Kangguo CHENG ,  Chen ZHANG ,  Wenyu XU

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A technique relates to a semiconductor device. A first vertical fin is formed with a first gate stack and a second vertical fin with a second gate stack. The second vertical fin has a hardmask on top. The first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region. The first gate stack is reduced to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask. The hardmask is removed. A first top S/D region is adjacent to the first vertical fin and a second top S/D region is adjacent to the second vertical fin.

公开(公告)号：US20190189739A1

公开(公告)日：2019-06-20

申请号：US15844725

申请日：2017-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juntao LI ,  Kangguo CHENG ,  Chen ZHANG ,  Xin MIAO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/161

Abstract: A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack.

公开(公告)号：US20190019811A1

公开(公告)日：2019-01-17

申请号：US16124291

申请日：2018-09-07

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Zuoguang LIU ,  Xin MIAO

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/285 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/84 ,  H01L29/66

Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

公开(公告)号：US20190006510A1

公开(公告)日：2019-01-03

申请号：US16112841

申请日：2018-08-27

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Xin MIAO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/161 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method for forming a semiconductor structure includes forming at least one fin on a semiconductor substrate. The least one fin includes a semiconducting material. A gate is formed over and in contact with the at least one fin. A germanium comprising layer is formed over and in contact with the at least one fin. Germanium from the germanium comprising layer is diffused into the semiconducting material of the at least one fin.

公开(公告)号：US20200176335A1

公开(公告)日：2020-06-04

申请号：US16781183

申请日：2020-02-04

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L21/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L29/786 ,  H01L21/683 ,  H01L21/84 ,  H01L23/50 ,  H01L23/528 ,  H01L27/12 ,  H01L21/8238

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

公开(公告)号：US20180219011A1

公开(公告)日：2018-08-02

申请号：US15937006

申请日：2018-03-27

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L23/535 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768

CPC classification number: H01L22/22 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/84 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L2221/68359

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

公开(公告)号：US20180122714A1

公开(公告)日：2018-05-03

申请号：US15848151

申请日：2017-12-20

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L21/66 ,  H01L21/683 ,  H01L27/12 ,  H01L23/50 ,  H01L21/84 ,  H01L23/528

CPC classification number: H01L27/0924 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/84 ,  H01L22/22 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L2221/68359

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.