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公开(公告)号：US20140089647A1
公开(公告)日：2014-03-27
申请号：US13625382
申请日：2012-09-24
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3005 , G06F9/30058 , G06F9/38 , G06F9/3844 , G06F9/3848
摘要： In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, a branch direction predictor may be updated responsive to a misprediction and also responsive to the branch prediction being within a threshold of transitioning between predictions. To avoid a lookup to determine if the threshold update is to be performed, the branch predictor may detect the threshold update during prediction, and may transmit an indication with the branch.
摘要翻译： 在一个实施例中，处理器可以被配置为从指令高速缓存（“取出组”）获取N个指令字节，即使获取组跨越高速缓存行边界。 分支预测器可以被配置为在获取组中产生多达M个分支的分支预测，其中M是可以包括在获取组中的最大分支数。 在一个实施例中，分支方向预测器可以响应于错误预测而被更新，并且还响应于在预测之间的转换阈值内的分支预测。 为了避免查找以确定是否要执行阈值更新，分支预测器可以在预测期间检测阈值更新，并且可以用分支发送指示。
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2.发明授权Branch predictor for wide issue, arbitrarily aligned fetch that can cross cache line boundaries 有权分支预测器，可以跨越高速缓存行边界进行广泛问题，任意对齐的提取公开(公告)号：US09201658B2
公开(公告)日：2015-12-01
申请号：US13625382
申请日：2012-09-24
CPC分类号： G06F9/3842 , G06F9/3005 , G06F9/30058 , G06F9/38 , G06F9/3844 , G06F9/3848
摘要： In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, branch prediction values from multiple entries in each table may be read and respective branch prediction values may be combined to form branch predictions for up to M branches in the fetch group.
摘要翻译： 在一个实施例中，处理器可以被配置为从指令高速缓存（“取出组”）获取N个指令字节，即使获取组跨越高速缓存行边界。 分支预测器可以被配置为在获取组中产生多达M个分支的分支预测，其中M是可以包括在获取组中的最大分支数。 在一个实施例中，可以读取每个表中来自多个条目的分支预测值，并且可以将相应的分支预测值组合以形成在取出组中多达M个分支的分支预测。
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公开(公告)号：US20130290681A1
公开(公告)日：2013-10-31
申请号：US13460178
申请日：2012-04-30
申请人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Sandeep Gupta
发明人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Sandeep Gupta
IPC分类号： G06F9/30
CPC分类号： G06F9/30141 , G06F1/3234 , G06F9/30112 , G06F9/384
摘要： A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.
摘要翻译： 一种有效降低寄存器文件访问功耗的系统和方法。 处理器可操作以执行具有两个或多个数据类型的指令，每个数据类型具有相关联的大小和对齐。 第一种数据类型的数据操作数使用等于物理寄存器文件中物理寄存器的整个宽度的操作数大小。 第二种数据类型的数据操作数使用小于物理寄存器整个宽度的操作数大小。 访问与非全宽数据类型相关的操作数的物理寄存器文件不能访问物理寄存器的全部宽度。 对于未访问的物理寄存器的部分，可以忽略给定的数值。
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公开(公告)号：US20130275720A1
公开(公告)日：2013-10-17
申请号：US13447651
申请日：2012-04-16
申请人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
发明人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
CPC分类号： G06F9/30032 , G06F9/384
摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.
摘要翻译： 一种用于减少数据移动操作的延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。 如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。 此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。 特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。
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公开(公告)号：US09575754B2
公开(公告)日：2017-02-21
申请号：US13447651
申请日：2012-04-16
申请人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
发明人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
CPC分类号： G06F9/30032 , G06F9/384
摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.
摘要翻译： 一种用于减少数据移动操作的延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。 如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。 此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。 特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。
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公开(公告)号：US09430243B2
公开(公告)日：2016-08-30
申请号：US13460268
申请日：2012-04-30
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3832 , G06F9/3857
摘要： A system and method for efficiently reducing the latency of initializing registers. A register rename unit within a processor determines whether prior to an execution pipeline stage it is known a decoded given instruction writes a particular numerical value in a destination operand. An example is a move immediate instruction that writes a value of 0 in its destination operand. Other examples may also qualify. If the determination is made, a given physical register identifier is assigned to the destination operand, wherein the given physical register identifier is associated with the particular numerical value, but it is not associated with an actual physical register in a physical register file. The given instruction is marked to prevent it from proceeding to an execution pipeline stage. When the given physical register identifier is used to read the physical register file, no actual physical register is accessed.
摘要翻译： 一种用于有效减少初始化寄存器的延迟的系统和方法。 处理器内的寄存器重命名单元确定在执行流水线阶段之前是否已知解码的给定指令将目标操作数中的特定数值写入。 一个示例是在其目标操作数中写入值0的移动即时指令。 其他示例也可能符合条件。 如果确定，给定的物理寄存器标识符被分配给目的地操作数，其中给定的物理寄存器标识符与特定数值相关联，但是它不与物理寄存器文件中的实际物理寄存器相关联。 给定的指令被标记为防止它进入执行流水线阶段。 当给定的物理寄存器标识符用于读取物理寄存器文件时，不会访问实际的物理寄存器。
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7.发明授权Instruction set architecture mode dependent sub-size access of register with associated status indication 有权指令集体系结构模式相关的子大小访问寄存器与相关状态指示公开(公告)号：US09317285B2
公开(公告)日：2016-04-19
申请号：US13460178
申请日：2012-04-30
申请人： Sandeep Gupta , Conrado Blasco-Allue , John H. Mylius , Gerard R. Williams, III , James B. Keller
发明人： Sandeep Gupta , Conrado Blasco-Allue , John H. Mylius , Gerard R. Williams, III , James B. Keller
CPC分类号： G06F9/30141 , G06F1/3234 , G06F9/30112 , G06F9/384
摘要： A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.
摘要翻译： 一种有效降低寄存器文件访问功耗的系统和方法。 处理器可操作以执行具有两个或多个数据类型的指令，每个数据类型具有相关联的大小和对齐。 第一种数据类型的数据操作数使用等于物理寄存器文件中物理寄存器的整个宽度的操作数大小。 第二种数据类型的数据操作数使用小于物理寄存器整个宽度的操作数大小。 访问与非全宽数据类型相关的操作数的物理寄存器文件不能访问物理寄存器的全部宽度。 对于未访问的物理寄存器的部分，可以忽略给定的数值。
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公开(公告)号：US20130290680A1
公开(公告)日：2013-10-31
申请号：US13460268
申请日：2012-04-30
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F9/3832 , G06F9/3857
摘要： A system and method for efficiently reducing the latency of initializing registers. A register rename unit within a processor determines whether prior to an execution pipeline stage it is known a decoded given instruction writes a particular numerical value in a destination operand. An example is a move immediate instruction that writes a value of 0 in its destination operand. Other examples may also qualify. If the determination is made, a given physical register identifier is assigned to the destination operand, wherein the given physical register identifier is associated with the particular numerical value, but it is not associated with an actual physical register in a physical register file. The given instruction is marked to prevent it from proceeding to an execution pipeline stage. When the given physical register identifier is used to read the physical register file, no actual physical register is accessed.
摘要翻译： 一种用于有效减少初始化寄存器的延迟的系统和方法。 处理器内的寄存器重命名单元确定在执行流水线阶段之前是否已知解码的给定指令将目标操作数中的特定数值写入。 一个示例是在其目标操作数中写入值0的移动即时指令。 其他示例也可能符合条件。 如果确定，给定的物理寄存器标识符被分配给目的地操作数，其中给定的物理寄存器标识符与特定数值相关联，但是它不与物理寄存器文件中的实际物理寄存器相关联。 给定的指令被标记为防止它进入执行流水线阶段。 当给定的物理寄存器标识符用于读取物理寄存器文件时，不会访问实际的物理寄存器。
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公开(公告)号：US09600289B2
公开(公告)日：2017-03-21
申请号：US13483268
申请日：2012-05-30
IPC分类号： G06F12/1018 , G06F12/0864 , G06F17/30 , G06F9/38 , G06F12/08 , G06F12/10
CPC分类号： G06F9/3834 , G06F9/3838 , G06F12/0864 , G06F12/1018 , G06F17/30949
摘要： Methods and processors for managing load-store dependencies in an out-of-order instruction pipeline. A load store dependency predictor includes a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes hashed values to identify load and store operations. When a load or store operation is detected, the PC and an architectural register number are used to create a hashed value that can be used to uniquely identify the operation. Then, the load store dependency predictor table is searched for any matching entries with the same hashed value.
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公开(公告)号：US20130339671A1
公开(公告)日：2013-12-19
申请号：US13517865
申请日：2012-06-14
CPC分类号： G06F9/30043 , G06F9/30181 , G06F9/3826 , G06F9/3834 , G06F9/3838 , G06F9/384
摘要： A system and method for reducing the latency of load operations. A register rename unit within a processor determines whether a decoded load instruction is eligible for conversion to a zero-cycle load operation. If so, control logic assigns a physical register identifier associated with a source operand of an older dependent store instruction to the destination operand of the load instruction. Additionally, the register rename unit marks the load instruction to prevent it from reading data associated with the source operand of the store instruction from memory. Due to the duplicate renaming, this data may be forwarded from a physical register file to instructions that are younger and dependent on the load instruction.
摘要翻译： 一种用于减少加载操作延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的加载指令是否符合转换为零周期加载操作的资格。 如果是这样，则控制逻辑将与旧的从属存储指令的源操作数相关联的物理寄存器标识分配给加载指令的目的地操作数。 此外，寄存器重命名单元标记加载指令以防止其从存储器读取与存储指令的源操作数相关联的数据。 由于重复重命名，该数据可能会从物理寄存器文件转发到更年轻且取决于加载指令的指令。
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