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    Data relay apparatus and semiconductor integrated circuit having the same
    1.
    发明授权
    Data relay apparatus and semiconductor integrated circuit having the same 失效
    数据中继装置及具有该数据中继装置的半导体集成电路

    公开(公告)号：US08139703B2

    公开(公告)日：2012-03-20

    申请号：US12038616

    申请日：2008-02-27

    申请人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    发明人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    IPC分类号： H03D3/24

    CPC分类号： H03K5/135 ,  H03L7/06

    摘要： A data relay apparatus according to one embodiment described herein can include a phase detection unit that can detect a phase difference between a clock output from a transmitter and a clock output from a receiver, and generate a plurality of phase detection signals, a data relay control unit that can distinguish a difference in clock timing between the clocks of the transmitter and the receiver in response to the plurality of phase detection signals, and output a relay data selection signal and a relay control clock, and a data relay unit that can transmit data output from the receiver to the transmitter in response to the relay data selection signal and the relay control clock.

    摘要翻译： 根据本文所述的一个实施例的数据中继装置可以包括相位检测单元，其可以检测从发送器输出的时钟与从接收器输出的时钟之间的相位差，并且生成多个相位检测信号，数据中继控制 单元，其可以响应于所述多个相位检测信号来区分发射机和接收机的时钟之间的时钟定时的差异，并且输出中继数据选择信号和中继控制时钟，以及可以发送数据的数据中继单元 响应于继电器数据选择信号和继电器控制时钟从接收器输出到发送器。

    DELAY LOCKED LOOP CIRCUIT OF SEMICONDUCTOR DEVICE
    4.
    发明申请
    DELAY LOCKED LOOP CIRCUIT OF SEMICONDUCTOR DEVICE 有权
    半导体器件的延迟锁定环路电路

    公开(公告)号：US20090116306A1

    公开(公告)日：2009-05-07

    申请号：US12262517

    申请日：2008-10-31

    申请人： Hee-Woong SONG ,  Kun-Woo Park ,  Yong-Ju Kim ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    发明人： Hee-Woong SONG ,  Kun-Woo Park ,  Yong-Ju Kim ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    IPC分类号： G11C7/00 ,  G11C8/18 ,  H03L7/06

    CPC分类号： G11C29/02 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03L7/0812 ,  H03L7/089 ,  H03L7/095

    摘要： A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.

    摘要翻译： 半导体存储器件包括可以根据高频系统时钟控制数据的输入/输出定时的延迟锁定环电路。 半导体存储装置包括：相位比较器，被配置为检测内部时钟和参考时钟之间的相位差，以输出具有与检测到的相位差相对应的脉冲宽度的状态信号;相位调整器，被配置为生成用于确定 对应于用于锁定内部时钟的相位的状态信号的延迟时间，配置成将数字代码转换为模拟电压的数模转换器，以及被配置为根据偏置来延迟内部时钟的多相延迟信号发生器 对应于模拟电压的电压反馈延迟的内部时钟作为内部时钟，并产生多相延迟信号。

    Delay locked loop circuit of semiconductor device
    5.
    发明授权
    Delay locked loop circuit of semiconductor device 有权
    半导体器件的延迟锁定环路

    公开(公告)号：US07990785B2

    公开(公告)日：2011-08-02

    申请号：US12262517

    申请日：2008-10-31

    申请人： Hee-Woong Song ,  Kun-Woo Park ,  Yong-Ju Kim ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    发明人： Hee-Woong Song ,  Kun-Woo Park ,  Yong-Ju Kim ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C29/02 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03L7/0812 ,  H03L7/089 ,  H03L7/095

    摘要： A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.

    摘要翻译： 半导体存储器件包括可以根据高频系统时钟控制数据的输入/输出定时的延迟锁定环电路。 半导体存储装置包括：相位比较器，被配置为检测内部时钟和参考时钟之间的相位差，以输出具有与检测到的相位差相对应的脉冲宽度的状态信号;相位调整器，被配置为生成用于确定 对应于用于锁定内部时钟的相位的状态信号的延迟时间，配置成将数字代码转换为模拟电压的数模转换器，以及被配置为根据偏置来延迟内部时钟的多相延迟信号发生器 对应于模拟电压的电压反馈延迟的内部时钟作为内部时钟，并产生多相延迟信号。

    Receiver circuit for use in a semiconductor integrated circuit
    6.
    发明授权
    Receiver circuit for use in a semiconductor integrated circuit 失效
    用于半导体集成电路的接收器电路

    公开(公告)号：US07868663B2

    公开(公告)日：2011-01-11

    申请号：US12171214

    申请日：2008-07-10

    申请人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    发明人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    IPC分类号： G01R19/00 ,  G11C7/00 ,  H03F3/45

    CPC分类号： H04L7/0337

    摘要： A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier.

    摘要翻译： 一种接收机电路，用于与具有相互不同相位的多个时钟信号同步地感测和发送输入数据，其顺序地使能，包括读出放大器，其被配置为接收作为偏移电压的第一信号，所述第一信号可以通过与 所述多个时钟信号的第一时钟信号与与所述第一时钟信号之后使能的第二时钟信号同步地驱动，并输出第二信号;以及放电控制器，被配置为根据所述偏移来控制所述读出放大器的放电速度 电压来控制读出放大器的驱动速度。

    Data output circuit for semiconductor memory apparatus
    7.
    发明授权
    Data output circuit for semiconductor memory apparatus 有权
    半导体存储装置的数据输出电路

    公开(公告)号：US07808841B2

    公开(公告)日：2010-10-05

    申请号：US12169568

    申请日：2008-07-08

    申请人： Hae-Rang Choi ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Ji-Wang Lee

    发明人： Hae-Rang Choi ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Ji-Wang Lee

    IPC分类号： G11C7/10 ,  G11C7/06 ,  G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/50

    摘要： A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver units being two or more times as much as the number of driver units in the first driver. A voltage level on the output node is the voltage level of an output signal.

    摘要翻译： 一种用于半导体存储装置的数据输出电路，包括具有多个控制信号生成单元的驱动器控制信号生成单元，每个控制信号生成单元响应于测试期间的测试信号生成驱动单元控制信号，并且生成驱动单元 根据在测试完成之后是否切断熔丝的控制信号，具有多个驱动单元的第一驱动器，每个驱动器单元响应于驱动单元控制信号被激活以驱动第一数据信号作为输入 信号并将驱动的第一数据信号输出到输出节点;响应于驱动单元控制信号和使能信号产生第一驱动器控制信号的信号组合单元，以及具有多个驱动器单元的第二驱动器， 其中的每一个响应于第一驱动器控制信号被激活，以驱动第二数据信号作为输入信号，并将驱动的第二数据信号输出到输出节点;以及 驱动器单元的数量是第一驱动器中的驱动器单元的数量的两倍或更多倍。 输出节点上的电压电平是输出信号的电压电平。

    DATA RELAY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME
    10.
    发明申请
    DATA RELAY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME 失效
    数据继电器和半导体集成电路

    公开(公告)号：US20090092215A1

    公开(公告)日：2009-04-09

    申请号：US12038616

    申请日：2008-02-27

    申请人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    发明人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    IPC分类号： H04L7/00

    CPC分类号： H03K5/135 ,  H03L7/06

    摘要： A data relay apparatus according to one embodiment described herein can include a phase detection unit that can detect a phase difference between a clock output from a transmitter and a clock output from a receiver, and generate a plurality of phase detection signals, a data relay control unit that can distinguish a difference in clock timing between the clocks of the transmitter and the receiver in response to the plurality of phase detection signals, and output a relay data selection signal and a relay control clock, and a data relay unit that can transmit data output from the receiver to the transmitter in response to the relay data selection signal and the relay control clock.

    摘要翻译： 根据本文所述的一个实施例的数据中继装置可以包括相位检测单元，其可以检测从发送器输出的时钟与从接收器输出的时钟之间的相位差，并且生成多个相位检测信号，数据中继控制 单元，其可以响应于所述多个相位检测信号来区分发射机和接收机的时钟之间的时钟定时的差异，并且输出中继数据选择信号和中继控制时钟，以及可以发送数据的数据中继单元 响应于继电器数据选择信号和继电器控制时钟从接收器输出到发送器。