摘要:
A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.
摘要:
A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.
摘要:
The present invention provides a semiconductor memory which can reduce the area of a circuit for replacing defective memory cells with redundant memory cells as well as reduce the time for writing defect information. The semiconductor memory of the present invention comprises a memory cell array 1 comprising (n+1) (n is a positive integer) word lines, a register unit 4 holding an encoded defect address for specifying a defective word line, a defect address decoder 31 for decoding the defect address from the register unit 4 to specify the defective word line, selection means S1˜Sn for selecting, for the i-th (1≦i≦n) output signal line of a row decoder 2, one of the i-th and i+1-th word lines and connecting the selected word line to the i-th output signal line, and control means C1˜Cn each controlling corresponding one of the selection means S1˜Sn on the basis of an output of the defect address decoder 31 so as to select, for the output signal line of the row decoder 2, one of the word lines except the defective word line in accordance with the arrangement order.
摘要:
A semiconductor integrated circuit includes a booster for boosting a power supply voltage, and outputting the boosted voltage; an output circuit being supplied with the boosted voltage, and generating an output voltage from the boosted voltage; a reference voltage generator being supplied with the power supply voltage, and generating a reference voltage from the power supply voltage; a voltage divider being supplied with the output voltage from the output circuit, and dividing the output voltage with a predetermined voltage ratio; and a differential amplifier being supplied with the reference voltage and the divided voltage, and controlling the output circuit by supplying the output circuit with a voltage obtained by performing differential amplification on the reference voltage and the divided voltage according to the power supply voltage, thereby maintaining the output voltage from the output circuit at a predetermined voltage. In this circuit, since the reference voltage generator and the differential amplifier are operated with the power supply voltage, it is not necessary to supply the boosted voltage to them, whereby the output current from the booster is reduced. Therefore, undesired reduction in the boosted voltage due to an increase in the output current is suppressed. As the result, the capacitance used in the booster is reduced, and the area of the semiconductor integrated circuit is reduced.
摘要:
A semiconductor memory device having nonvolatile memory cells arranged in matrix comprises and bit lines connected to drains of the memory cells. Latches provided for the respective bit lines or in the ratio of one latch to a number of bit lines, as are; transfer gates for electrically separating the respective latches from the bit lines. The device also having bit line voltage detection circuits for detecting voltages of the respective bit lines and latch reset circuits for inverting data stored in the respective latches in accordance with the outputs from the bit line voltage detection circuits. Therefore, data stored in each latch can be rewritten even by a very small memory cell current, resulting in stable program verify.
摘要:
In the circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and input data representing waveforms with time of voltages or currents used for operation simulation, and storing the circuit diagram data to memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary voltage/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.
摘要:
There is provided a nonvolatile semiconductor memory which is capable of operating stably and performing high-speed access operation. A timing generation means 51 for generating timing signals which make a memory core unit 4 perform access operation uses first and second clocks of the same cycle and different phases. The timing generation means 51 generates timing signals for at least one first-half event among a plurality of read access events, according to the first clock, the phase of which precedes a phases of the second clock, and generates timing signals used for processing the remaining events, according to the second clock.
摘要:
An arithmetic decoding device comprises an adaptive arithmetic decoding unit, a context calculating unit, and a decoding control unit. The adaptive arithmetic decoding unit includes an arithmetic decoding unit, a symbol appearing probability control unit, and a probability state storing unit. When a variable-length encoded code (VLC) is inputted, the context calculating unit generates a context number from a classification and a decoded bit number of a syntax element of the inputted code, and outputs the context number to the adaptive arithmetic decoding unit. The adaptive arithmetic decoding unit renews a symbol appearing probability based on the frequency of appearance of the symbol, thereby arithmetic-decoding the inputted code (VLC), and feeding output data (OD). The decoding control unit controls the whole arithmetic decoding device.
摘要:
The position of a body part area for a personal image in an input image is detected. According to the position of the detected body part area, the position of the origin of a coordinate system for an ornament image is defined. Based on the position of the defined origin, an ornament-arranged input image is outputted. When the personal image moves in the input image, the ornament image also moves by following the movement of the personal image. Even when both the personal image and ornament image move, the ornament image can be made not to interfere with the personal image. Therefore, the personal image can be clearly displayed. Moreover, the input image can be made to look more interesting by synchronizing the movement of the ornament image with the movement of the personal image.
摘要:
A frame brightness detecting unit 15 detects a frame brightness value of each of a plurality of image frames. A flicker spectrum detecting unit 16 detects, from the frame brightness values of 512 frames, spectrum values at frequencies, such as 100 Hz, 200 Hz, and 300 Hz. A brightness estimating unit 17 estimates a brightens value of a light source from the spectrum values. An encoding unit 18 uses a reciprocal of the estimated brightens value to determine a reference frame. The encoding unit 18 also uses the reciprocal in an evaluation function for motion vector estimation. The image frame is encoded using the motion vector.