公开(公告)号：US08867259B2

公开(公告)日：2014-10-21

申请号：US13704649

申请日：2012-08-09

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh ,  Shunsaku Muraoka

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh ,  Shunsaku Muraoka

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/56 ,  G11C2213/79

摘要： A method of programming a variable resistance nonvolatile memory element that removes a defect in a resistance change, ensures an operation widow, and stably sustains a resistance change operation, the method including: applying, when the detect in the resistance change occurs in the variable resistance nonvolatile memory element, a recovery voltage pulse at least once to the variable resistance nonvolatile memory element, the recovery voltage pulse including: a first recovery voltage pulse that has an amplitude greater than amplitudes of a normal high resistance writing voltage pulse and a low resistance writing voltage pulse; and a second recovery voltage pulse that is the low resistance writing voltage pulse following the first recovery voltage pulse.

摘要翻译： 一种编程消除电阻变化缺陷的可变电阻非易失性存储元件的方法，确保操作遗ow，并稳定地维持电阻变化操作，该方法包括：当在可变电阻中发生电阻变化的检测时， 非易失性存储元件，至少一次到可变电阻非易失性存储元件的恢复电压脉冲，恢复电压脉冲包括：第一恢复电压脉冲，其具有大于正常高电阻写入电压脉冲和低电阻写入的幅度的幅度 电压脉冲; 以及第二恢复电压脉冲，其是跟随第一恢复电压脉冲的低电阻写入电压脉冲。

公开(公告)号：US08325508B2

公开(公告)日：2012-12-04

申请号：US13001905

申请日：2010-06-08

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

IPC分类号： G11C11/00

CPC分类号： G11C11/5685 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/56 ,  G11C2213/79

摘要： A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value. At the HR writing step (S51a), a voltage pulse having a voltage Vp that is equal to or higher than the first voltage V1 and equal to or lower than the second voltage V2 is applied to the variable resistance element, thereby changing the variable resistance element from the low resistance state (S52) to the high resistance state (S53).

摘要翻译： 提供了一种最佳可变电阻元件的写入方法，其可以使可变电阻元件的操作窗口最大化。 对于根据施加的电压脉冲的极性在高电阻状态和低电阻状态之间可逆地变化的可变电阻元件执行写入方法。 写入方法包括准备步骤（S50）和写入步骤（S51，S51a，S51b）。 在准备步骤（S50）中，通过向可变电阻元件施加逐渐增加的电压的电压脉冲来测量可变电阻元件的电阻值，从而确定用于开始高电阻写入的第一电压V1和具有 最大电阻值。 在HR写入步骤（S51a）中，将具有等于或高于第一电压V1并且等于或低于第二电压V2的电压Vp的电压脉冲施加到可变电阻元件，从而改变可变电阻 元件从低电阻状态（S52）到高电阻状态（S53）。

公开(公告)号：US20120230085A1

公开(公告)日：2012-09-13

申请号：US13511275

申请日：2011-09-28

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Koji Katayama ,  Shunsaku Muraoka

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Koji Katayama ,  Shunsaku Muraoka

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier (303) for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FF1 to FFn and a clock signal CLK. Thereby, a switch transistor (301) is in a non-conducting state and the forming on a variable resistance element is automatically terminated.

摘要翻译： 在形成时，包括在非易失性存储器件（200）中的自动形成电路（210）使得恒定电流IL流过具有相当高的初始电阻的所选择的存储单元。 当形成在存储单元中产生细丝通路并由此电阻值减小时，节点NBL的电位和节点Nin的电位也减小。 如果电位变得低于参考电压Vref的电位，则激活用于检测成形成功的差分放大器（303）的输出NO，并且根据触发器的数量n在延迟时间之后激活形成成功信号Vfp FF1〜FFn和时钟信号CLK。 由此，开关晶体管（301）处于非导通状态，可变电阻元件上的形成自动终止。

公开(公告)号：US20110216577A1

公开(公告)日：2011-09-08

申请号：US13126257

申请日：2010-08-26

申请人： Hiroshi Tomotani ,  Kazuhiko Shimakawa ,  Ken Kawai

发明人： Hiroshi Tomotani ,  Kazuhiko Shimakawa ,  Ken Kawai

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/10 ,  H01L45/00 ,  H01L49/00

摘要： The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element (100) in the low resistance state, performs stable operations, and includes an LR write circuit (500) (i) applying a voltage to a memory cell (102) so that a resistance state of the variable resistance element included in the memory cell is changed from high to low, and (ii) including a first driving circuit (510) and a second driving circuit (520) which apply voltages to the memory cell and which have connected output terminals. When applying a voltage to the memory cell, the first driving circuit supplies a first current, and the second driving circuit (i) supplies a second current when a voltage at the output terminal of the first driving circuit is higher than a reference voltage VREF, and (ii) is in a high impedance state when the voltage is lower than the VREF.

摘要翻译： 可变电阻非易失性存储装置减小了在低电阻状态下的可变电阻元件（100）的电阻值的变化，执行稳定的操作，并且包括LR写入电路（500）（i）向存储单元施加电压 102），使得包含在存储单元中的可变电阻元件的电阻状态从高变为低，并且（ii）包括向存储器施加电压的第一驱动电路（510）和第二驱动电路（520） 并具有连接的输出端子。 当向存储单元施加电压时，第一驱动电路提供第一电流，并且当第一驱动电路的输出端的电压高于参考电压VREF时，第二驱动电路（i）提供第二电流， 和（ii）当电压低于VREF时处于高阻抗状态。

公开(公告)号：US20050232013A1

公开(公告)日：2005-10-20

申请号：US11080424

申请日：2005-03-16

申请人： Ken Kawai ,  Takafumi Maruyama

发明人： Ken Kawai ,  Takafumi Maruyama

IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C16/02 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  H02M3/335

CPC分类号： G11C8/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454 ,  G11C16/3459

摘要： A plurality of switches composing a voltage changing switch circuit 17 are supplied with a plurality of types of voltages, and are provided so as to correspond to a plurality of row decoders 2, such that each switch can separately select and output any of the plurality of types of voltages to the corresponding row decoder 2. Voltage boost circuits 7, 8 generate a plurality of types of voltages by boosting a power supply voltage. A regulator circuit 9 steps down at least one of the plurality of types of voltages generated by the voltage boost circuits 7, 8 to stabilize a voltage value, and outputs the resultant voltage to each switch. Each row decoder 2 selects a memory cell by using a voltage outputted from the corresponding switch. Thus, it is possible to reduce a time required for a program/program verify operation, while reducing power consumption.

摘要翻译： 构成电压变化开关电路17的多个开关被提供有多种类型的电压，并且被设置为对应于多个行解码器2，使得每个开关可以分开地选择和输出多个 电压类型到相应行解码器2.升压电路7,8通过升高电源电压而产生多种类型的电压。 调节器电路9降压由升压电路7,8产生的多种类型的电压中的至少一种，以稳定电压值，并将所得到的电压输出到每个开关。 每行解码器2通过使用从相应的开关输出的电压来选择存储单元。 因此，可以减少程序/程序验证操作所需的时间，同时降低功耗。

公开(公告)号：US09378817B2

公开(公告)日：2016-06-28

申请号：US13581925

申请日：2012-03-22

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/0092

摘要： A variable resistance nonvolatile memory element writing method of, by applying a voltage pulse to a memory cell including a variable resistance element, reversibly changing the variable resistance element between a first resistance state and a second resistance state according to a polarity of the applied voltage pulse is provided. The variable resistance nonvolatile memory element writing method includes applying a first preliminary voltage pulse and subsequently applying the first voltage pulse to the variable resistance element to change the variable resistance element from the second resistance state to the first resistance state, the first preliminary voltage pulse being smaller in voltage absolute value than the second threshold voltage and different in polarity from the first voltage pulse.

摘要翻译： 一种可变电阻非易失性存储元件写入方法，通过向包括可变电阻元件的存储单元施加电压脉冲，根据所施加的电压脉冲的极性可逆地改变第一电阻状态和第二电阻状态之间的可变电阻元件 被提供。 可变电阻非易失性存储元件写入方法包括施加第一初步电压脉冲，并随后将第一电压脉冲施加到可变电阻元件，以将可变电阻元件从第二电阻状态改变到第一电阻状态，第一初步电压脉冲为 电压绝对值比第二阈值电压小，并且极性与第一电压脉冲不同。

公开(公告)号：US20140112054A1

公开(公告)日：2014-04-24

申请号：US13983314

申请日：2012-11-13

申请人： Kazuhiko Shimakawa ,  Akifumi Kawahara ,  Ryotaro Azuma ,  Ken Kawai

发明人： Kazuhiko Shimakawa ,  Akifumi Kawahara ,  Ryotaro Azuma ,  Ken Kawai

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0038

摘要： A sense amplification circuit includes a sneak current compensating load current supply unit that selectively switches a load current among load currents having different current amounts and supplies the load current to a bit line selected by a column selection circuit. The sense amplification circuit outputs ‘L’ level when a current amount of the load current is more than a reference current amount, and outputs ‘H’ level when the current amount is less than the reference current amount. A control circuit adjusts the current amount to a predetermined current amount that causes the sense amplification circuit to output ‘H’ level. After the adjustment, the control circuit performs control to supply the load current having the predetermined current amount and controls the writing unit to keep the application until the sense amplification circuit outputs ‘L’ level.

摘要翻译： 感测放大电路包括潜流补偿负载电流供应单元，其选择性地切换具有不同电流量的负载电流之间的负载电流，并将负载电流提供给由列选择电路选择的位线。 当负载电流的当前量大于参考电流量时，感测放大电路输出“L”电平，当电流量小于基准电流量时，输出“H”电平。 控制电路将电流量调整到使得感测放大电路输出“H”电平的预定电流量。 在调整之后，控制电路进行控制以提供具有预定电流量的负载电流，并且控制写入单元以保持应用直到读出放大电路输出“L”电平。

公开(公告)号：US08625328B2

公开(公告)日：2014-01-07

申请号：US13126257

申请日：2010-08-26

申请人： Hiroshi Tomotani ,  Kazuhiko Shimakawa ,  Ken Kawai

发明人： Hiroshi Tomotani ,  Kazuhiko Shimakawa ,  Ken Kawai

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/10 ,  H01L45/00 ,  H01L49/00

摘要： The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element (100) in the low resistance state, performs stable operations, and includes an LR write circuit (500) (i) applying a voltage to a memory cell (102) so that a resistance state of the variable resistance element included in the memory cell is changed from high to low, and (ii) including a first driving circuit (510) and a second driving circuit (520) which apply voltages to the memory cell and which have connected output terminals. When applying a voltage to the memory cell, the first driving circuit supplies a first current, and the second driving circuit (i) supplies a second current when a voltage at the output terminal of the first driving circuit is higher than a reference voltage VREF, and (ii) is in a high impedance state when the voltage is lower than the VREF.

摘要翻译： 可变电阻非易失性存储装置减小了在低电阻状态下的可变电阻元件（100）的电阻值的变化，执行稳定的操作，并且包括LR写入电路（500）（i）向存储单元施加电压 102），使得包含在存储单元中的可变电阻元件的电阻状态从高变为低，并且（ii）包括向存储器施加电压的第一驱动电路（510）和第二驱动电路（520） 并具有连接的输出端子。 当向存储单元施加电压时，第一驱动电路提供第一电流，并且当第一驱动电路的输出端的电压高于参考电压VREF时，第二驱动电路（i）提供第二电流， 和（ii）当电压低于VREF时处于高阻抗状态。

公开(公告)号：US08395925B2

公开(公告)日：2013-03-12

申请号：US13001943

申请日：2010-06-04

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： An optimum forming method of performing a forming for a variable resistance element to maximize an operation window of the variable resistance element is provided. The forming method is used to initialize a variable resistance element (100). The forming method includes: a determination step (S35) of determining whether or not a current resistance value of the variable resistance element (100) is lower than a resistance value in a high resistance state; and a voltage application step (S36) of applying a voltage pulse having a voltage not exceeding a sum of a forming voltage and a forming margin when the determination is made that the current resistance value is not lower than the resistance value in the high resistance state (No at S35). The determination step (S35) and the voltage application step (S36) are repeated to process all memory cells in a memory array (202) (S34 to S37).

摘要翻译： 提供了一种用于对可变电阻元件进行成形以最大化可变电阻元件的操作窗口的最佳形成方法。 成形方法用于初始化可变电阻元件（100）。 形成方法包括：确定可变电阻元件（100）的当前电阻值是否低于高电阻状态下的电阻值的确定步骤（S35） 以及当确定当前电阻值不低于高电阻状态下的电阻值时，施加具有不超过形成电压和形成余量之和的电压的电压脉冲的电压施加步骤（S36） （S35否）。 重复确定步骤（S35）和电压施加步骤（S36）以处理存储器阵列（202）中的所有存储器单元（S34至S37）。

公开(公告)号：US20110110144A1

公开(公告)日：2011-05-12

申请号：US13001905

申请日：2010-06-08

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

IPC分类号： G11C11/21

CPC分类号： G11C11/5685 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/56 ,  G11C2213/79

摘要： A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value. At the HR writing step (S51a), a voltage pulse having a voltage Vp that is equal to or higher than the first voltage V1 and equal to or lower than the second voltage V2 is applied to the variable resistance element, thereby changing the variable resistance element from the low resistance state (S52) to the high resistance state (S53).

摘要翻译： 提供了一种最佳可变电阻元件的写入方法，其可以使可变电阻元件的操作窗口最大化。 对于根据施加的电压脉冲的极性在高电阻状态和低电阻状态之间可逆地变化的可变电阻元件执行写入方法。 写入方法包括准备步骤（S50）和写入步骤（S51，S51a，S51b）。 在准备步骤（S50）中，通过向可变电阻元件施加逐渐增加的电压的电压脉冲来测量可变电阻元件的电阻值，从而确定用于开始高电阻写入的第一电压V1和具有 最大电阻值。 在HR写入步骤（S51a）中，将具有等于或高于第一电压V1并且等于或低于第二电压V2的电压Vp的电压脉冲施加到可变电阻元件，从而改变可变电阻 元件从低电阻状态（S52）到高电阻状态（S53）。