利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.024 秒)

    Pre-tracing instructions for CGA coupled processor in inactive mode for execution upon switch to active mode and continuing pre-fetching cache miss instructions
    6.
    发明授权
    Pre-tracing instructions for CGA coupled processor in inactive mode for execution upon switch to active mode and continuing pre-fetching cache miss instructions 有权
    CGA耦合处理器在非活动模式下的预跟踪指令，用于在切换到活动模式并继续预取高速缓存未命中指令时执行

    公开(公告)号：US07836277B2

    公开(公告)日：2010-11-16

    申请号：US12042868

    申请日：2008-03-05

    申请人： Il Hyun Park ,  Dong-Hoon Yoo ,  Dong Kwan Suh ,  Soojung Ryu ,  Jeongwook Kim

    发明人： Il Hyun Park ,  Dong-Hoon Yoo ,  Dong Kwan Suh ,  Soojung Ryu ,  Jeongwook Kim

    IPC分类号： G06F9/06

    CPC分类号： G06F9/3808 ,  G06F9/322 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/6028

    摘要： A method of managing an instruction cache and a process of using the method are provided. The processor may comprise a processor core which is operated either during an active mode or during an inactive mode wherein the process core performs at least one instruction during the active mode, an instruction cache which pre-traces a first instruction and determines, during the inactive mode, whether the processor core will meet a cache miss with regard to the first instruction, wherein the first instruction is to be performed by the processor core during the active mode, a coarse-grained array which performs a second instruction during the inactive mode, and a configuration memory which stores configuration information of the coarse-grained array, wherein the coarse-grained array performs the second instruction using the configuration information.

    摘要翻译： 提供了一种管理指令高速缓存的方法和使用该方法的过程。 处理器可以包括在活动模式期间或在非活动模式期间操作的处理器核心，其中处理核心在活动模式期间执行至少一个指令，指令高速缓存器，其在非活动模式期间预跟踪第一指令并确定 模式，处理器核心是否将满足关于第一指令的高速缓存未命中，其中在活动模式期间由处理器核心执行第一指令，在非活动模式期间执行第二指令的粗粒度阵列， 以及配置存储器，其存储粗粒度阵列的配置信息，其中粗粒子阵列使用配置信息执行第二指令。

    Cache memory system using temporal locality information and a data storage method
    8.
    发明授权
    Cache memory system using temporal locality information and a data storage method 有权
    高速缓冲存储器系统使用时间局部性信息和数据存储方法

    公开(公告)号：US08793437B2

    公开(公告)日：2014-07-29

    申请号：US11835635

    申请日：2007-08-08

    申请人： Jong Myon Kim ,  Soojung Ryu ,  Dong-Hoon Yoo ,  Dong Kwan Suh ,  Jeongwook Kim

    发明人： Jong Myon Kim ,  Soojung Ryu ,  Dong-Hoon Yoo ,  Dong Kwan Suh ,  Jeongwook Kim

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F12/0897 ,  G06F12/123

    摘要： A cache memory system using temporal locality information and a data storage method are provided. The cache memory system including: a main cache which stores data accessed by a central processing unit; an extended cache which stores the data if the data is evicted from the main cache; and a separation cache which stores the data of the extended cache when the data of the extended cache is evicted from the extended cache and temporal locality information corresponding to the data of the extended cache satisfies a predetermined condition.

    摘要翻译： 提供了一种使用时间局部性信息和数据存储方法的缓存存储器系统。 高速缓冲存储器系统包括：主缓存器，其存储由中央处理单元访问的数据; 如果数据从主缓存中逐出，则存储数据的扩展高速缓存; 以及分离高速缓存，当扩展高速缓冲存储器的数据从扩展高速缓存中逐出时存储扩展高速缓存的数据，并且与扩展高速缓冲存储器的数据相对应的时间位置信息满足预定条件。

    Memory access method using three dimensional address mapping
    9.
    发明授权
    Memory access method using three dimensional address mapping 有权
    内存访问方法使用三维地址映射

    公开(公告)号：US07779225B2

    公开(公告)日：2010-08-17

    申请号：US11828440

    申请日：2007-07-26

    申请人： Jong Myon Kim ,  Soojung Ryu ,  Dong-Hoon Yoo ,  Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Kyoung June Min

    发明人： Jong Myon Kim ,  Soojung Ryu ,  Dong-Hoon Yoo ,  Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Kyoung June Min

    IPC分类号： G06F12/00

    CPC分类号： G06F8/443 ,  G06F8/447 ,  G06F12/0207

    摘要： A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining an a×b×c number of addresses of the memory accessed by the triple loop using the starting address and a function.

    摘要翻译： 存储器访问方法包括：从程序中用于访问具有三重循环的存储器的程序代码获取a，b和c，所述三循环的最内循环变量可以具有多个值，b 是三重循环的中间循环变量可能具有的多个值，c是三重循环的最外圈循环变量可能具有的值的数量; 获取由三重循环访问的存储器的起始地址; 并使用起始地址和功能获得由三重回路访问的存储器的a×b×c个地址。

    Processor and method of performing speculative load operations of the processor
    10.
    发明授权
    Processor and method of performing speculative load operations of the processor 有权
    处理器和执行处理器的推测加载操作的方法

    公开(公告)号：US08443174B2

    公开(公告)日：2013-05-14

    申请号：US11838488

    申请日：2007-08-14

    申请人： Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Suk Jin Kim

    发明人： Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Suk Jin Kim

    IPC分类号： G06F9/30 ,  G06F9/312

    CPC分类号： G06F9/3842

    摘要： Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor.

    摘要翻译： 提供了一种执行处理器的推测性加载指令的处理器和方法，其中仅在加载指令基本访问存储器的情况下执行加载指令。 在除了上述情况之外的其他情况下执行用于取消操作的加载指令，使得仅在执行推测性加载指令时访问输入/输出（I / O）映射存储区等而出现的问题可以仅被使用 一种类似软件的方法，从而提高处理器的性能。