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    Reverse polarity protection for n-substrate high-side switches
    3.
    发明授权
    Reverse polarity protection for n-substrate high-side switches 有权
    n基板高边开关的反极性保护

    公开(公告)号：US09245888B2

    公开(公告)日：2016-01-26

    申请号：US13631924

    申请日：2012-09-29

    Applicant: Infineon Technologies AG

    Inventor： Luca Petruzzi ,  Bernhard Auer ,  Paolo Del Croce ,  Markus Ladurner

    IPC: H01L29/78 ,  H01L27/092 ,  H01L27/02 ,  H03K17/0814 ,  H01L29/423

    CPC classification number: H01L27/0922 ,  H01L27/0248 ,  H01L29/42368 ,  H01L29/7813 ,  H01L2924/0002 ,  H03K17/08142 ,  H01L2924/00

    Abstract: A semiconductor device is disclosed. In accordance with a first aspect of the present invention the device includes a semiconductor chip having a substrate, a first supply terminal electrically coupled to the substrate to provide a first supply potential (VS) and a load current to the substrate, and a second supply terminal operably provided with a second supply potential. A first vertical transistor is integrated in the semiconductor chip and electrically coupled between the supply terminal and an output terminal. The first vertical transistor is configured to provide a current path for the load current to the output terminal in accordance with a control signal, which is provided to a gate electrode of the first vertical transistor.

    Abstract translation: 公开了一种半导体器件。 根据本发明的第一方面，该器件包括具有衬底的半导体芯片，与衬底电耦合以提供第一电源电位（VS）和向衬底提供负载电流的第一电源端子，以及第二电源 端子可操作地设置有第二电源电位。 第一垂直晶体管集成在半导体芯片中并电耦合在电源端子和输出端子之间。 第一垂直晶体管被配置为根据提供给第一垂直晶体管的栅电极的控制信号为输出端提供负载电流的电流路径。

    Semiconductor Device Having First and Second Circuits Integrated in a Semiconductor Body
    4.
    发明申请
    Semiconductor Device Having First and Second Circuits Integrated in a Semiconductor Body 审中-公开

    公开(公告)号：US20170309739A1

    公开(公告)日：2017-10-26

    申请号：US15646496

    申请日：2017-07-11

    Applicant: Infineon Technologies AG

    Inventor： Norbert Krischke ,  Bernhard Auer ,  Robert Illing

    IPC: H01L29/78 ,  H01L29/40

    CPC classification number: H01L29/7803 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7815

    Abstract: A semiconductor device includes at least one wiring layer disposed on a semiconductor body, a field effect transistor integrated in the semiconductor body, the field effect transistor having a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body, a first circuit integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit integrated in the semiconductor body and remote from the first circuit. The semiconductor device further includes a first additional trench formed in the semiconductor body and at least one conductive pad formed in the at least one wiring layer. The first additional trench includes at least one connecting line which electrically connects the first circuit and the second circuit. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

    Semiconductor Switch with Integrated Temperature Sensor
    6.
    发明申请
    Semiconductor Switch with Integrated Temperature Sensor 有权
    具有集成温度传感器的半导体开关

    公开(公告)号：US20160071972A1

    公开(公告)日：2016-03-10

    申请号：US14840925

    申请日：2015-08-31

    Applicant: Infineon Technologies AG

    Inventor： Norbert Krischke ,  Bernhard Auer ,  Robert Illing

    IPC: H01L29/78

    CPC classification number: H01L29/7803 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7815

    Abstract: A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

    Abstract translation: 半导体器件包括半导体本体，设置在半导体本体上的至少一个布线层和集成在半导体本体中的场效应晶体管。 场效应晶体管具有驻留在半导体本体中形成的相应栅极沟槽中的多个栅电极。 第一电路集成在与场效应晶体管相邻的半导体本体中，并且第二电路集成在远离第一电路的半导体本体中。 第一附加沟槽形成在半导体本体中，并且包括至少一个电连接第一电路和第二电路的连接线。 半导体器件还包括形成在至少一个布线层中的至少一个导电焊盘。 所述至少一个导电垫被布置成至少部分地覆盖所述第一附加沟槽以形成所述至少一个连接线的屏蔽。

    INTELLIGENT SEMICONDUCTOR SWITCH WITH QUASI-DIGITAL CURRENT LIMITATION
    7.
    发明公开
    INTELLIGENT SEMICONDUCTOR SWITCH WITH QUASI-DIGITAL CURRENT LIMITATION 审中-公开

    公开(公告)号：US20240204766A1

    公开(公告)日：2024-06-20

    申请号：US18528469

    申请日：2023-12-04

    Applicant: Infineon Technologies AG

    Inventor： Christian Djelassi-Tscheck ,  Alexander Mayer ,  Mario Tripolt ,  Vincent Thiery ,  Markus Huebl ,  Bernhard Auer

    IPC: H03K17/082 ,  H03K17/687

    CPC classification number: H03K17/0822 ,  H03K17/687 ,  H03K2217/0027 ,  H03K2217/0036

    Abstract: A current limitation concept for an intelligent semiconductor switch is described herein. In accordance with one embodiment, a method performed by the intelligent semiconductor switch comprises generating a gate current and switching on a power transistor by applying the gate current to the gate electrode of the power transistor. The method further comprises determining information regarding a load current passing through the power transistor and controlling—based on the information regarding the load current—the load current by reducing the gate current applied to the gate electrode of the power transistor. When the load current exceeds a first threshold value, the gate current is reduced by a specific amount, and when the load current exceeds a third threshold value, the gate current is further reduced by sinking a discharge current, which has a third current level, from the gate electrode of the power transistor.

    Integrated circuit (IC) chip arrangement
    9.
    发明授权
    Integrated circuit (IC) chip arrangement 有权

    公开(公告)号：US10580762B1

    公开(公告)日：2020-03-03

    申请号：US16170761

    申请日：2018-10-25

    Applicant: Infineon Technologies AG

    Inventor： Christian Djelassi-Tscheck ,  Bernhard Auer ,  Markus Ladurner

    IPC: H01L23/52 ,  H01L25/16 ,  H01L23/495 ,  H01L23/00 ,  H01L25/00

    Abstract: Examples disclosed herein involve integrated circuit chip arrangements. An example integrated circuit (IC) package may include a first semiconductor chip that includes a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second semiconductor chip mounted within a housing of the IC package. The second semiconductor chip may include a second MOSFET and a control circuit configured with a first driver for the first MOSFET and a second driver for the second MOSFET. The first semiconductor chip may be mounted to the second semiconductor chip opposite a base of the IC package.

    Semiconductor switch with integrated temperature sensor
    10.
    发明授权
    Semiconductor switch with integrated temperature sensor 有权

    公开(公告)号：US09735264B2

    公开(公告)日：2017-08-15

    申请号：US14840925

    申请日：2015-08-31

    Applicant: Infineon Technologies AG

    Inventor： Norbert Krischke ,  Bernhard Auer ,  Robert Illing

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40

    CPC classification number: H01L29/7803 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7815

    Abstract: A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

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