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    Bandgap curvature correction
    1.
    发明授权
    Bandgap curvature correction 有权

    公开(公告)号：US10175711B1

    公开(公告)日：2019-01-08

    申请号：US15699055

    申请日：2017-09-08

    Applicant: Infineon Technologies AG

    Inventor： Luca Petruzzi ,  Anthony Candage

    IPC: G05F3/26

    Abstract: In some examples, a device includes a curvature-correction circuit including a first current source configured to generate a PTAT electrical current. In some examples, the curvature-correction circuit also includes three or more programmable current sources configured to generate three or more programmable electrical currents. In some examples, the curvature-correction circuit is configured to generate a PWL electrical current based on the PTAT electrical current and the three or more programmable electrical currents. In some examples, the device also includes a reference voltage circuit configured to generate a reference voltage signal based on the PWL electrical current.

    On chip reverse polarity protection compliant with ISO and ESD requirements
    3.
    发明授权
    On chip reverse polarity protection compliant with ISO and ESD requirements 有权
    片上反极性保护符合ISO和ESD要求

    公开(公告)号：US09472948B2

    公开(公告)日：2016-10-18

    申请号：US14042155

    申请日：2013-09-30

    Applicant: Infineon Technologies AG

    Inventor： Luca Petruzzi

    IPC: H02H9/04 ,  H01L27/02 ,  H01L29/78 ,  H01L21/761 ,  H01L29/866 ,  H01L27/092

    CPC classification number: H02H9/041 ,  H01L21/761 ,  H01L27/0248 ,  H01L27/0921 ,  H01L27/0922 ,  H01L29/7835 ,  H01L29/866 ,  H02H9/043

    Abstract: A semiconductor device is disclosed. In one embodiment a semiconductor device includes a semiconductor chip including a substrate, a ground terminal configured to be provided with a reference potential and a supply terminal electrically coupled to the substrate, the supply terminal configured to be provided with a load current and configured to be provided with a supply voltage between the substrate and the ground terminal. The semiconductor device further comprises an overvoltage protection circuit disposed in the semiconductor chip and coupled between the supply terminal and the ground terminal, the overvoltage protection circuit including a first transistor having a load current path coupled between the supply terminal and an internal ground node and a second transistor having a load current path coupled between the internal ground node and the ground terminal.

    Abstract translation: 公开了一种半导体器件。 在一个实施例中，半导体器件包括：半导体芯片，其包括衬底，配置成具有参考电位的接地端子和电耦合到衬底的供电端子，所述供电端子被配置为具有负载电流并且被配置为 在基板和接地端子之间提供电源电压。 所述半导体器件还包括设置在所述半导体芯片中并耦合在所述电源端子和所述接地端子之间的过电压保护电路，所述过电压保护电路包括第一晶体管，所述第一晶体管具有耦合在所述电源端子和内部接地节点之间的负载电流路径， 第二晶体管具有耦合在内部接地节点和接地端子之间的负载电流路径。

    Minority Carrier Conversion Structure
    5.
    发明申请
    Minority Carrier Conversion Structure 有权
    少数载体转换结构

    公开(公告)号：US20160056280A1

    公开(公告)日：2016-02-25

    申请号：US14466198

    申请日：2014-08-22

    Applicant: Infineon Technologies AG

    Inventor： Adrian Finney ,  Paolo Del Croce ,  Luca Petruzzi ,  Norbert Krischke

    IPC: H01L29/78 ,  H01L27/06 ,  H01L29/06

    CPC classification number: H01L29/7811 ,  H01L21/765 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/0922 ,  H01L29/0607 ,  H01L29/0688 ,  H01L29/7805

    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.

    Abstract translation: 根据半导体器件的实施例，半导体器件在半导体衬底中包括良好的功率器件，在衬底中良好的逻辑器件，并且通过衬底的分离区与阱与阱的间隔开，并且少数载流子转换 在分离区域中包括第一导电类型的第一掺杂区域，在分离区域中具有第二导电类型的第二掺杂区域和连接第一和第二掺杂区域的导电层。 第二掺杂区域包括插入在第一掺杂区域和功率器件阱之间的第一部分和插入在第一掺杂区域和逻辑器件阱之间的第二部分。

    Switch device and method
    8.
    发明授权
    Switch device and method 有权

    公开(公告)号：US10454469B2

    公开(公告)日：2019-10-22

    申请号：US15840194

    申请日：2017-12-13

    Applicant: Infineon Technologies AG

    Inventor： Francesca Romano ,  Alexander Mayer ,  Luca Petruzzi

    IPC: H03K17/18 ,  H03K17/30 ,  H03K17/16 ,  H03K17/081

    Abstract: An embodiment method includes detecting an inverse current condition at a switch, and driving a node associated with a switch driver driving the switch to a predetermined voltage in response to the detection of an inverse current condition at the switch. An embodiment switch device includes a switch driver configured to be coupled to a control terminal of a switch, an inverse current detector configured to detect an inverse current condition at the first and second load terminals of the switch, and a voltage driver configured to drive a node associated with the switch driver to a predetermined voltage in response to the inverse current detector detecting an inverse current condition.

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