ERROR-TOLERANT MEMORIES
    2.
    发明申请
    ERROR-TOLERANT MEMORIES 有权
    错误的记忆

    公开(公告)号:US20130339819A1

    公开(公告)日:2013-12-19

    申请号:US13914073

    申请日:2013-06-10

    CPC classification number: G06F11/08 G06F11/1008 H03K19/0033 H03K19/23

    Abstract: Methods and apparatuses relating to error-tolerant memories are provided. In one example embodiment, output signals from at least three memory devices are supplied to an error correction device. The error correction device outputs a corrected data value in such a manner that, when the read data values match, this data value is output and, in at least one state in which the data values do not match, a previously output data value is retained.

    Abstract translation: 提供了与容错存储器相关的方法和装置。 在一个示例实施例中,来自至少三个存储器装置的输出信号被提供给纠错装置。 错误校正装置输出校正数据值,使得当读取的数据值匹配时,输出该数据值,并且在数据值不匹配的至少一个状态中保留先前输出的数据值 。

    Error-tolerant memories
    4.
    发明授权
    Error-tolerant memories 有权
    容错记忆

    公开(公告)号:US09424124B2

    公开(公告)日:2016-08-23

    申请号:US13914073

    申请日:2013-06-10

    CPC classification number: G06F11/08 G06F11/1008 H03K19/0033 H03K19/23

    Abstract: Methods and apparatuses relating to error-tolerant memories are provided. In one example embodiment, output signals from at least three memory devices are supplied to an error correction device. The error correction device outputs a corrected data value in such a manner that, when the read data values match, this data value is output and, in at least one state in which the data values do not match, a previously output data value is retained.

    Abstract translation: 提供了与容错存储器相关的方法和装置。 在一个示例实施例中,来自至少三个存储器装置的输出信号被提供给纠错装置。 错误校正装置输出校正数据值,使得当读取的数据值匹配时,输出该数据值,并且在数据值不匹配的至少一个状态中保留先前输出的数据值 。

    Devices and methods for data storage

    公开(公告)号:US11327835B2

    公开(公告)日:2022-05-10

    申请号:US16944697

    申请日:2020-07-31

    Abstract: In an embodiment, a storage device includes a multiplicity of data value memory cells and a multiplicity of check value memory cells, where at least one of the multiplicity of data value memory cells is assigned to two of the check value memory cells, and where at least one of the multiplicity of check value memory cells is assigned to two of the data value memory cells, and a correction circuit which is configured to output a corrected data value when reading out a selected data value memory cell of the at least one of the multiplicity of data value memory cells, based on a content of the selected data value memory cell and based on contents of the two check value memory cells assigned to the selected data value memory cell.

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