公开(公告)号：US20220230919A1

公开(公告)日：2022-07-21

申请号：US17575000

申请日：2022-01-13

Applicant: Infineon Technologies AG

Inventor： Fabian CRAES ,  Wolfgang LEHNERT ,  Maik LOHMANN ,  Harry Walter SAX

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package is provided. The method may include singulating a wafer including a plurality of dies fixed to an auxiliary carrier to generate dies having released side surfaces, covering at least the side surfaces of the dies with a passivation layer using a deposition process at a temperature below the melting temperature of the auxiliary carrier, keeping a gap between the passivation layers at the side surfaces of adjacent dies of the plurality of dies.

公开(公告)号：US20210375792A1

公开(公告)日：2021-12-02

申请号：US17333186

申请日：2021-05-28

Applicant: Infineon Technologies AG

Inventor： Harry Walter SAX ,  Johann GATTERBAUER ,  Wolfgang LEHNERT ,  Evelyn NAPETSCHNIG ,  Michael ROGALLI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

公开(公告)号：US20230395532A1

公开(公告)日：2023-12-07

申请号：US18236858

申请日：2023-08-22

Applicant: Infineon Technologies AG

Inventor： Harry Walter SAX ,  Johann GATTERBAUER ,  Wolfgang LEHNERT ,  Evelyn NAPETSCHNIG ,  Michael ROGALLI

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/564 ,  H01L24/05 ,  H01L24/03 ,  H01L23/3142 ,  H01L21/56 ,  H01L2924/365 ,  H01L2224/05687 ,  H01L2224/0382

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

公开(公告)号：US20240371796A1

公开(公告)日：2024-11-07

申请号：US18774379

申请日：2024-07-16

Applicant: Infineon Technologies AG

Inventor： Harry Walter SAX ,  Johann GATTERBAUER ,  Wolfgang LEHNERT ,  Evelyn NAPETSCHNIG ,  Michael ROGALLI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

公开(公告)号：US20230064442A1

公开(公告)日：2023-03-02

申请号：US17879900

申请日：2022-08-03

Applicant: Infineon Technologies AG

Inventor： Chan Whai Augustine KAN ,  Martin MAYER ,  Edmund RIEDL ,  Edward FUERGUT ,  Harry Walter SAX

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/42 ,  H01L23/00

Abstract: A chip package structure is disclosed. In one example, the chip package may include a chip, an encapsulation material, and an exposed pad that is electrically conductively connected to the chip. A layer of a porous or dendrite-comprising adhesion promoter is on a surface of the exposed pad. A thermal interface material that is attached to the exposed pad by the layer.