公开(公告)号：US20240371796A1

公开(公告)日：2024-11-07

申请号：US18774379

申请日：2024-07-16

Applicant: Infineon Technologies AG

Inventor： Harry Walter SAX ,  Johann GATTERBAUER ,  Wolfgang LEHNERT ,  Evelyn NAPETSCHNIG ,  Michael ROGALLI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

公开(公告)号：US20230154978A1

公开(公告)日：2023-05-18

申请号：US17526490

申请日：2021-11-15

Applicant: Infineon Technologies AG

Inventor： Carsten SCHAEFFER ,  Patrick HANEKAMP ,  Oliver HUMBEL ,  Angelika KOPROWSKI ,  Wolfgang LEHNERT ,  Francisco Javier SANTOS RODRIGUEZ

IPC: H01L29/06 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L29/0638 ,  H01L29/402 ,  H01L21/0217 ,  H01L21/02118 ,  H01L21/0228

Abstract: A semiconductor device and a method of forming a semiconductor device are provided. In an embodiment, the semiconductor device comprises a device region, an edge termination region surrounding the device region, a first metal feature in the edge termination region, a first conformal ion diffusion barrier layer over the first metal feature, and a first conformal chemical protection layer over the first conformal ion diffusion barrier layer.

公开(公告)号：US20220230919A1

公开(公告)日：2022-07-21

申请号：US17575000

申请日：2022-01-13

Applicant: Infineon Technologies AG

Inventor： Fabian CRAES ,  Wolfgang LEHNERT ,  Maik LOHMANN ,  Harry Walter SAX

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package is provided. The method may include singulating a wafer including a plurality of dies fixed to an auxiliary carrier to generate dies having released side surfaces, covering at least the side surfaces of the dies with a passivation layer using a deposition process at a temperature below the melting temperature of the auxiliary carrier, keeping a gap between the passivation layers at the side surfaces of adjacent dies of the plurality of dies.

公开(公告)号：US20230395532A1

公开(公告)日：2023-12-07

申请号：US18236858

申请日：2023-08-22

Applicant: Infineon Technologies AG

Inventor： Harry Walter SAX ,  Johann GATTERBAUER ,  Wolfgang LEHNERT ,  Evelyn NAPETSCHNIG ,  Michael ROGALLI

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/564 ,  H01L24/05 ,  H01L24/03 ,  H01L23/3142 ,  H01L21/56 ,  H01L2924/365 ,  H01L2224/05687 ,  H01L2224/0382

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

公开(公告)号：US20210159115A1

公开(公告)日：2021-05-27

申请号：US17104559

申请日：2020-11-25

Applicant: Infineon Technologies AG

Inventor： Werner SCHUSTEREDER ,  Alexander BREYMESSER ,  Mihai DRAGHICI ,  Tobias Franz Wolfgang HOECHBAUER ,  Wolfgang LEHNERT ,  Hans-Joachim SCHULZE ,  Marko David SWOBODA

IPC: H01L21/762 ,  H01L21/3115 ,  H01L21/265 ,  H01L21/768

Abstract: Methods for processing a semiconductor substrate are proposed. An example of a method includes forming cavities in the semiconductor substrate by implanting ions through a first surface of the semiconductor substrate. The cavities define a separation layer in the semiconductor substrate. A semiconductor layer is formed on the first surface of the semiconductor substrate. Semiconductor device elements are formed in the semiconductor layer. The semiconductor substrate is separated along the separation layer into a first substrate part including the semiconductor layer and a second substrate part.

公开(公告)号：US20250006814A1

公开(公告)日：2025-01-02

申请号：US18756389

申请日：2024-06-27

Applicant: Infineon Technologies AG

Inventor： Wolfgang LEHNERT ,  Fabian RASINGER ,  Thomas AICHINGER ,  Gerald RESCHER ,  Francisco Javier SANTOS RODRIGUEZ ,  Carsten SCHAEFFER ,  Armin TILKE

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/16 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78

Abstract: A method for forming an interface layer on a silicon carbide body comprises removing an oxide layer from a surface of a silicon carbide body to obtain a silicon carbide surface. The silicon carbide body comprises a source region of a first conductivity type and a body region of a second conductivity type. The method further comprises after removing the oxide layer, depositing an interface layer directly on the silicon carbide surface. The interface layer has a thickness of less or equal to 15 nm. The method further comprises forming an electrical insulator over the interface layer, and forming a gate electrode over the electrical insulator.

公开(公告)号：US20240405092A1

公开(公告)日：2024-12-05

申请号：US18664904

申请日：2024-05-15

Applicant: Infineon Technologies AG

Inventor： Armin TILKE ,  Sandra KRAUSE ,  Thomas AICHINGER ,  Wolfgang LEHNERT ,  Francisco Javier SANTOS RODRIGUEZ

IPC: H01L29/51 ,  H01L29/16 ,  H01L29/423

Abstract: There is described a semiconductor device comprising an SiC body with a gate structure comprising a gate dielectric with a specific multilayer laminate structure including alternating layers of a first dielectric material and of a second dielectric material having a dielectric constant of 4 or higher. There is further described a method for manufacturing such a semiconductor device including an SiC body as mentioned before.

公开(公告)号：US20210375792A1

公开(公告)日：2021-12-02

申请号：US17333186

申请日：2021-05-28

Applicant: Infineon Technologies AG

Inventor： Harry Walter SAX ,  Johann GATTERBAUER ,  Wolfgang LEHNERT ,  Evelyn NAPETSCHNIG ,  Michael ROGALLI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.