公开(公告)号：US20150325535A1

公开(公告)日：2015-11-12

申请号：US14272535

申请日：2014-05-08

Applicant: Infineon Technologies AG

Inventor： Stephan HENNECK ,  Evelyn NAPETSCHNIG ,  Daniel PEDONE ,  Bernhard WEIDGANS ,  Simon FAISS ,  Ivan NIKITIN

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03472 ,  H01L2224/03614 ,  H01L2224/05007 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05583 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/01023

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.

Abstract translation: 根据各种实施例的用于处理半导体器件的方法可以包括：在半导体工件上沉积第一金属化层; 图案化第一金属化层; 以及在图案化的第一金属化层上沉积第二金属化层，其中沉积第二金属化层包括无电沉积工艺，包括将图案化的第一金属化层浸入金属电解质中。

公开(公告)号：US20230395532A1

公开(公告)日：2023-12-07

申请号：US18236858

申请日：2023-08-22

Applicant: Infineon Technologies AG

Inventor： Harry Walter SAX ,  Johann GATTERBAUER ,  Wolfgang LEHNERT ,  Evelyn NAPETSCHNIG ,  Michael ROGALLI

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/564 ,  H01L24/05 ,  H01L24/03 ,  H01L23/3142 ,  H01L21/56 ,  H01L2924/365 ,  H01L2224/05687 ,  H01L2224/0382

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

公开(公告)号：US20240371796A1

公开(公告)日：2024-11-07

申请号：US18774379

申请日：2024-07-16

Applicant: Infineon Technologies AG

Inventor： Harry Walter SAX ,  Johann GATTERBAUER ,  Wolfgang LEHNERT ,  Evelyn NAPETSCHNIG ,  Michael ROGALLI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

公开(公告)号：US20210167034A1

公开(公告)日：2021-06-03

申请号：US17149741

申请日：2021-01-15

Applicant: Infineon Technologies AG

Inventor： Manfred MENGEL ,  Alexander HEINRICH ,  Steffen ORSO ,  Thomas BEHRENS ,  Oliver EICHINGER ,  Lim FONG ,  Evelyn NAPETSCHNIG ,  Edmund RIEDL

IPC: H01L23/00 ,  B23K35/30 ,  B23K35/26 ,  B23K35/28 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/495 ,  B23K1/00

Abstract: A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.

公开(公告)号：US20240347369A1

公开(公告)日：2024-10-17

申请号：US18605019

申请日：2024-03-14

Applicant: Infineon Technologies AG

Inventor： Frank SINGER ,  Thorsten SCHARF ,  Evelyn NAPETSCHNIG

IPC: H01L21/683 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L21/6836 ,  H01L21/568 ,  H01L21/60 ,  H01L2021/6006 ,  H01L2221/68318 ,  H01L2221/68354

Abstract: A method is disclosed. In one example, the method comprises mounting an electronic component on an adhesive base structure on a temporary carrier, and dissolving at least part of the base structure by irradiating the base structure with electromagnetic radiation to thereby release the electronic component.

公开(公告)号：US20210375792A1

公开(公告)日：2021-12-02

申请号：US17333186

申请日：2021-05-28

Applicant: Infineon Technologies AG

Inventor： Harry Walter SAX ,  Johann GATTERBAUER ,  Wolfgang LEHNERT ,  Evelyn NAPETSCHNIG ,  Michael ROGALLI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

公开(公告)号：US20170323865A1

公开(公告)日：2017-11-09

申请号：US15659670

申请日：2017-07-26

Applicant: Infineon Technologies AG

Inventor： Manfred MENGEL ,  Alexander HEINRICH ,  Steffen ORSO ,  Thomas BEHRENS ,  Oliver EICHINGER ,  Lim FONG ,  Evelyn NAPETSCHNIG ,  Edmund RIEDL

IPC: H01L23/00 ,  B23K35/28 ,  B23K35/30 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/495 ,  B23K1/00 ,  C22C30/04 ,  B23K35/26

CPC classification number: H01L24/48 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/282 ,  B23K35/3013 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/207

Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

公开(公告)号：US20170316934A1

公开(公告)日：2017-11-02

申请号：US15141855

申请日：2016-04-29

Applicant: Infineon Technologies AG

Inventor： Evelyn NAPETSCHNIG ,  Sandra WIRTITSCH ,  Mario BARUSIC ,  Aleksander HINZ ,  Robert HARTL ,  Georg SCHINNER

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/306 ,  H01L21/225 ,  H01L29/167

CPC classification number: H01L21/02068 ,  H01L21/02082 ,  H01L21/0209 ,  H01L21/221 ,  H01L21/2251 ,  H01L21/30604 ,  H01L21/3247 ,  H01L29/167

Abstract: According to various embodiments, a method for processing a semiconductor region, wherein the semiconductor region comprises at least one precipitate, may include: forming a precipitate removal layer over the semiconductor region, wherein the precipitate removal layer may define an absorption temperature at which a chemical solubility of a constituent of the at least one precipitate is greater in the precipitate removal layer than in the semiconductor region; and heating the at least one precipitate above the absorption temperature.