公开(公告)号：US20230187298A1

公开(公告)日：2023-06-15

申请号：US18107800

申请日：2023-02-09

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Thomas Fischer ,  Uwe Seidel ,  Anton Steltenpohl

IPC: H01L23/31

CPC classification number: H01L23/3164 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L21/6836 ,  H01L2924/10335

Abstract: A package includes: an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and an encapsulant encapsulating the dielectric layer and the semiconductor die. The encapsulant is a mold compound having different material properties than the dielectric layer. A method of manufacturing package is also described.

公开(公告)号：US20210335687A1

公开(公告)日：2021-10-28

申请号：US17237143

申请日：2021-04-22

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Thomas Fischer ,  Uwe Seidel ,  Anton Steltenpohl

IPC: H01L23/31

Abstract: An electronic component includes a mold layer and a semiconductor die including a low ohmic first portion and a high ohmic second portion. The low ohmic first portion has an active area. The high ohmic second portion is arranged on the mold layer.

公开(公告)号：US10985041B2

公开(公告)日：2021-04-20

申请号：US16220888

申请日：2018-12-14

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Gerald Lackner ,  Walter Horst Leitgeb ,  Michael Lecher

IPC: H01L21/67 ,  G01B11/27 ,  H01L21/68 ,  H01L21/78 ,  H01L21/66

Abstract: A method and apparatus for use in a wafer processing are disclosed. In an embodiment a includes providing the wafer on a receptacle, wherein the receptacle comprises a light port, and wherein the light port includes a source of light, shining a light from the source of light at an edge of the wafer thereby passing light by the edge of the wafer and processing the wafer on the receptacle based on the light passing by the edge of the wafer and received by a light sensitive element.

公开(公告)号：US10600670B2

公开(公告)日：2020-03-24

申请号：US15860687

申请日：2018-01-03

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/67 ,  H01L21/687 ,  B28D5/00

Abstract: An apparatus which comprises an expansion unit configured for expanding a foil, and a mounting unit configured for subsequently mounting the expanded foil on a frame and a workpiece, in particular a wafer, on the expanded foil.

公开(公告)号：US20170133253A1

公开(公告)日：2017-05-11

申请号：US14933931

申请日：2015-11-05

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Gerald Lackner ,  Walter Horst Leitgeb ,  Michael Lecher

IPC: H01L21/67 ,  G01B11/27 ,  H01L21/68 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L21/67259 ,  G01B11/272 ,  H01L21/67092 ,  H01L21/681 ,  H01L21/78 ,  H01L22/20

Abstract: A method and an apparatus for use in processing a wafer are disclosed. In an embodiment the method includes providing a wafer on a receptacle, shining a light at an edge of the wafer and based on light that passed the edge of the wafer, processing the wafer on the receptacle.

公开(公告)号：US09484316B2

公开(公告)日：2016-11-01

申请号：US14070334

申请日：2013-11-01

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Ulrike Fastner ,  Alexander Heinrich ,  Thomas Fischer

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683

CPC classification number: H01L24/05 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02205 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/11011 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11845 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/26125 ,  H01L2224/27009 ,  H01L2224/27019 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/27845 ,  H01L2224/29007 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01032 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Abstract translation: 根据本发明的实施例，形成半导体器件的方法包括在衬底的第一主表面上形成接触层。 衬底包括由切口区域分隔开的器件区域。 接触层设置在切口区域和器件区域中。 在器件区域上形成结构化的焊料层。 在形成结构化的焊料层之后，在切割区域处露出接触层。 切割区域中的接触层和基底。

公开(公告)号：US09293371B2

公开(公告)日：2016-03-22

申请号：US14748260

申请日：2015-06-24

Applicant: Infineon Technologies AG

Inventor： Anja Reitmeier ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

公开(公告)号：US20150294911A1

公开(公告)日：2015-10-15

申请号：US14748260

申请日：2015-06-24

Applicant: Infineon Technologies AG

Inventor： Anja Reitmeier ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/78 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

Abstract translation: 提供了一种用于处理半导体工件的方法，其可以包括：提供包括设置在半导体工件侧面的金属化层堆叠的半导体工件，金属化层堆叠包括至少第一层和设置在第一层上的第二层 层，其中所述第一层包含第一材料，并且所述第二层包含不同于所述第一材料的第二材料; 图案化金属化层堆叠，其中图案化金属化层堆叠包括通过蚀刻溶液湿法蚀刻第一层和第二层，蚀刻溶液对于第一材料和第二材料具有至少基本上相同的蚀刻速率。

公开(公告)号：US20250029884A1

公开(公告)日：2025-01-23

申请号：US18904744

申请日：2024-10-02

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Thomas Fischer ,  Uwe Seidel ,  Anton Steltenpohl

IPC: H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29

Abstract: A method of manufacturing a package that includes providing an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer. The semiconductor die having an active area with monolithically integrated circuit elements. Encapsulating the dielectric layer and the semiconductor die by an encapsulant. The encapsulant is a mold compound having different material properties than the dielectric layer, and the dielectric layer includes a polymer.

公开(公告)号：US12112992B2

公开(公告)日：2024-10-08

申请号：US18107800

申请日：2023-02-09

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Thomas Fischer ,  Uwe Seidel ,  Anton Steltenpohl

IPC: H01L23/31 ,  H01L21/683 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L23/3164 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L21/6836 ,  H01L23/295 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2221/68327 ,  H01L2221/68368 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335

Abstract: A package includes: an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and an encapsulant encapsulating the dielectric layer and the semiconductor die. The encapsulant is a mold compound having different material properties than the dielectric layer. A method of manufacturing package is also described.