公开(公告)号：US10732201B2

公开(公告)日：2020-08-04

申请号：US14251610

申请日：2014-04-13

Applicant: Infineon Technologies AG

Inventor： Kok Kiat Koo

IPC: G01R1/067

Abstract: A test probe for testing a chip package is provided, wherein the test probe comprises a test probe body comprising a conductive material; and a probe tip arranged on an end of the test probe body and comprising carbon nano tubes.

公开(公告)号：US20180190557A1

公开(公告)日：2018-07-05

申请号：US15397270

申请日：2017-01-03

Applicant: Infineon Technologies AG

Inventor： Upendra Balehithlu Manjappaiah ,  Kok Kiat Koo ,  Khai Seen Yong

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/28 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/49555 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/1815 ,  H01L2224/32245 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a first contact element, a second contact element, a semiconductor chip, and an encapsulation material. The first contact element is on a first side of the semiconductor device. The second contact element is on a second side of the semiconductor device opposite to the first side. The semiconductor chip is electrically coupled to the first contact element and the second contact element. The encapsulation material encapsulates the semiconductor chip and portions of the first contact element and the second contact element. The encapsulation material defines at least two notches on a third side of the semiconductor device extending between the first side and the second side.

公开(公告)号：US10483178B2

公开(公告)日：2019-11-19

申请号：US15397270

申请日：2017-01-03

Applicant: Infineon Technologies AG

Inventor： Upendra Balehithlu Manjappaiah ,  Kok Kiat Koo ,  Khai Seen Yong

IPC: H01L23/31 ,  H01L23/28 ,  H01L21/48 ,  H01L23/495

Abstract: A semiconductor device includes a first contact element, a second contact element, a semiconductor chip, and an encapsulation material. The first contact element is on a first side of the semiconductor device. The second contact element is on a second side of the semiconductor device opposite to the first side. The semiconductor chip is electrically coupled to the first contact element and the second contact element. The encapsulation material encapsulates the semiconductor chip and portions of the first contact element and the second contact element. The encapsulation material defines at least two notches on a third side of the semiconductor device extending between the first side and the second side.

公开(公告)号：US09082737B2

公开(公告)日：2015-07-14

申请号：US13678421

申请日：2012-11-15

Applicant: Infineon Technologies AG

Inventor： Carlo Baterna Marbella ,  Ganesh Vetrivel Periasamy ,  Woon Yik Yong ,  Kok Kiat Koo ,  Christian Arndt ,  Edward Myers

IPC: H01L23/34 ,  H01L23/495 ,  H01L25/16 ,  H01L23/31

CPC classification number: H01L23/34 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49555 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract translation: 公开了一种包括故障打开机构的半导体封装。 一个实施例包括具有芯片载体的半导体封装，设置在芯片载体上的芯片和封装芯片和芯片载体的密封剂。 所述半导体封装还包括从所述密封剂突出的销和设置在所述密封剂上并连接到所述销的故障开放机构，其中所述故障开启机构被配置为如果温度超过预定温度则与所述销断开。

公开(公告)号：US20140131844A1

公开(公告)日：2014-05-15

申请号：US13678421

申请日：2012-11-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Carlo Baterna Marbella ,  Ganesh Vetrivel Periasamy ,  Woon Yik Yong ,  Kok Kiat Koo ,  Christian Arndt ,  Edward Myers

IPC: H01L23/34 ,  H01L23/495

CPC classification number: H01L23/34 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49555 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract translation: 公开了一种包括故障打开机构的半导体封装。 一个实施例包括具有芯片载体的半导体封装，设置在芯片载体上的芯片和封装芯片和芯片载体的密封剂。 所述半导体封装还包括从所述密封剂突出的销和设置在所述密封剂上并连接到所述销的故障开放机构，其中所述故障开启机构被配置为如果温度超过预定温度则与所述销断开。