公开(公告)号：US20220278060A1

公开(公告)日：2022-09-01

申请号：US17746306

申请日：2022-05-17

Applicant: Infineon Technologies AG

Inventor： Shao Ping Wan ,  Eric Brion Acquitan ,  Dexter Reynoso ,  Jürgen Schredl ,  Woon Yik Yong

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A corresponding method of producing the molded semiconductor package also is described.

公开(公告)号：US20220181280A1

公开(公告)日：2022-06-09

申请号：US17113170

申请日：2020-12-07

Applicant: Infineon Technologies AG

Inventor： Shao Ping Wan ,  Eric Brion Acquitan ,  Dexter Reynoso ,  Jürgen Schredl ,  Woon Yik Yong

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A breakdown voltage of the electrically insulative material is greater than a breakdown voltage of the mold compound.

公开(公告)号：US11355460B1

公开(公告)日：2022-06-07

申请号：US17113170

申请日：2020-12-07

Applicant: Infineon Technologies AG

Inventor： Shao Ping Wan ,  Eric Brion Acquitan ,  Dexter Reynoso ,  Jürgen Schredl ,  Woon Yik Yong

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A breakdown voltage of the electrically insulative material is greater than a breakdown voltage of the mold compound.

公开(公告)号：US11444011B2

公开(公告)日：2022-09-13

申请号：US17095947

申请日：2020-11-12

Applicant: Infineon Technologies AG

Inventor： Woon Yik Yong ,  Andreas Kucher ,  Chia-Yen Lee ,  Shao Ping Wan

IPC: H01L23/495 ,  H01L23/00

Abstract: An embodiment of a semiconductor package includes a leadframe having leads, a mold compound partly encasing the leadframe so that the leads protrude from the mold compound, a power transistor die attached to the leadframe at a first side of the leadframe, and a driver die attached to the leadframe at a second side of the leadframe opposite the first side so that the power transistor die and the driver die are disposed in a stacked arrangement. The driver die is configured to control the power transistor die. The driver die is in direct electrical communication with the power transistor die only through the leadframe and any interconnects which attach the power transistor die and the driver die to the leadframe. Corresponding methods of manufacturing the semiconductor package are also described.

公开(公告)号：US20210066172A1

公开(公告)日：2021-03-04

申请号：US17095947

申请日：2020-11-12

Applicant: Infineon Technologies AG

Inventor： Woon Yik Yong ,  Andreas Kucher ,  Chia-Yen Lee ,  Shao Ping Wan

IPC: H01L23/495 ,  H01L23/00

Abstract: An embodiment of a semiconductor package includes a leadframe having leads, a mold compound partly encasing the leadframe so that the leads protrude from the mold compound, a power transistor die attached to the leadframe at a first side of the leadframe, and a driver die attached to the leadframe at a second side of the leadframe opposite the first side so that the power transistor die and the driver die are disposed in a stacked arrangement. The driver die is configured to control the power transistor die. The driver die is in direct electrical communication with the power transistor die only through the leadframe and any interconnects which attach the power transistor die and the driver die to the leadframe. Corresponding methods of manufacturing the semiconductor package are also described.

公开(公告)号：US11817407B2

公开(公告)日：2023-11-14

申请号：US17746306

申请日：2022-05-17

Applicant: Infineon Technologies AG

Inventor： Shao Ping Wan ,  Eric Brion Acquitan ,  Dexter Reynoso ,  Jürgen Schredl ,  Woon Yik Yong

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L21/565 ,  H01L23/3142 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0569 ,  H01L2924/301

Abstract: A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A corresponding method of producing the molded semiconductor package also is described.

公开(公告)号：US09082737B2

公开(公告)日：2015-07-14

申请号：US13678421

申请日：2012-11-15

Applicant: Infineon Technologies AG

Inventor： Carlo Baterna Marbella ,  Ganesh Vetrivel Periasamy ,  Woon Yik Yong ,  Kok Kiat Koo ,  Christian Arndt ,  Edward Myers

IPC: H01L23/34 ,  H01L23/495 ,  H01L25/16 ,  H01L23/31

CPC classification number: H01L23/34 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49555 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract translation: 公开了一种包括故障打开机构的半导体封装。 一个实施例包括具有芯片载体的半导体封装，设置在芯片载体上的芯片和封装芯片和芯片载体的密封剂。 所述半导体封装还包括从所述密封剂突出的销和设置在所述密封剂上并连接到所述销的故障开放机构，其中所述故障开启机构被配置为如果温度超过预定温度则与所述销断开。

公开(公告)号：US20140131844A1

公开(公告)日：2014-05-15

申请号：US13678421

申请日：2012-11-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Carlo Baterna Marbella ,  Ganesh Vetrivel Periasamy ,  Woon Yik Yong ,  Kok Kiat Koo ,  Christian Arndt ,  Edward Myers

IPC: H01L23/34 ,  H01L23/495

CPC classification number: H01L23/34 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49555 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract translation: 公开了一种包括故障打开机构的半导体封装。 一个实施例包括具有芯片载体的半导体封装，设置在芯片载体上的芯片和封装芯片和芯片载体的密封剂。 所述半导体封装还包括从所述密封剂突出的销和设置在所述密封剂上并连接到所述销的故障开放机构，其中所述故障开启机构被配置为如果温度超过预定温度则与所述销断开。