公开(公告)号：US09171766B2

公开(公告)日：2015-10-27

申请号：US13886407

申请日：2013-05-03

Applicant: Infineon Technologies AG

Inventor： Carlo Baterna Marbella

IPC: H01L21/66 ,  H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L22/30 ,  H01L21/4842 ,  H01L21/565 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/49555 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A lead frame strip includes a plurality of connected unit lead frames. Each unit lead frame has a die paddle for attaching to a semiconductor die, a tie bar connecting the die paddle to a periphery of the unit lead frame, and a plurality of leads projecting from the periphery toward the die paddle. The lead frame strip further includes a support member patterned into or connected to the periphery of each unit lead frame at a proximal end and bent into a different plane than the leads so that a distal end of each support member is disposed above or below the leads and projects toward the die paddles. The distal end of the support members can be anchored in a mold compound encapsulating electronic components attached to the die paddles, to maintain structural integrity during lead frame strip testing prior to unit lead frame separation.

Abstract translation: 引线框架条包括多个连接的单元引线框架。 每个单元引线框架具有用于连接到半导体管芯的管芯焊盘，将管芯焊盘连接到单元引线框架的周边的连接杆以及从周边朝向管芯焊盘突出的多个引线。 引线框架条还包括在近端处被图案化或连接到每个单元引线框架的周边并且弯曲成与引线不同的平面的支撑构件，使得每个支撑构件的远端设置在引线的上方或下方 并向模具桨投射。 支撑构件的远端可以锚固在封装连接到模板的电子部件的模具化合物中，以在单元引线框架分离之前的引线框条带测试期间保持结构完整性。

公开(公告)号：US20140327004A1

公开(公告)日：2014-11-06

申请号：US13886407

申请日：2013-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Carlo Baterna Marbella

IPC: H01L21/66

CPC classification number: H01L22/30 ,  H01L21/4842 ,  H01L21/565 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/49555 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A lead frame strip includes a plurality of connected unit lead frames. Each unit lead frame has a die paddle for attaching to a semiconductor die, a tie bar connecting the die paddle to a periphery of the unit lead frame, and a plurality of leads projecting from the periphery toward the die paddle. The lead frame strip further includes a support member patterned into or connected to the periphery of each unit lead frame at a proximal end and bent into a different plane than the leads so that a distal end of each support member is disposed above or below the leads and projects toward the die paddles. The distal end of the support members can be anchored in a mold compound encapsulating electronic components attached to the die paddles, to maintain structural integrity during lead frame strip testing prior to unit lead frame separation.

Abstract translation: 引线框架条包括多个连接的单元引线框架。 每个单元引线框架具有用于连接到半导体管芯的管芯焊盘，将管芯焊盘连接到单元引线框架的周边的连接杆以及从周边朝向管芯焊盘突出的多个引线。 引线框架条还包括在近端处被图案化或连接到每个单元引线框架的周边并且弯曲成与引线不同的平面的支撑构件，使得每个支撑构件的远端设置在引线的上方或下方 并向模具桨投射。 支撑构件的远端可以锚固在封装连接到模板的电子部件的模具化合物中，以在单元引线框架分离之前的引线框条带测试期间保持结构完整性。

公开(公告)号：US20150131249A1

公开(公告)日：2015-05-14

申请号：US14077642

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Carlo Baterna Marbella ,  Fabian Schnoy

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K3/3452 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09045 ,  H05K2201/09909 ,  H05K2201/10734

Abstract: A board for mechanically supporting and electrically connecting electronic components includes a non-conductive substrate, a plurality of electrically conductive traces and pads disposed on the non-conductive substrate, and a solder mask applied to the non-conductive substrate and covering the traces. Metal lines are disposed on the non-conductive substrate under the solder mask and along at least two sides of the pads disposed in corners of the non-conductive substrate, so that a metal line is interposed between the pads in the corners of the non-conductive substrate and each adjacent pad. The metal lines form a raised region in the solder mask along the metal lines which prevents solder bridging in the corners of the non-conductive substrate during solder reflow. A corresponding semiconductor package and semiconductor assembly with such solder bridging prevention structures are also provided.

Abstract translation: 用于机械地支撑和电连接电子部件的板包括非导电衬底，设置在非导电衬底上的多个导电迹线和焊盘，以及施加到非导电衬底并覆盖迹线的焊接掩模。 金属线设置在焊接掩模下面的非导电衬底上，并且沿着设置在非导电衬底的拐角中的焊盘的至少两侧，使得金属线插入在非导电衬底的角部的焊盘之间， 导电基板和每个相邻的垫。 金属线沿着金属线在焊料掩模中形成凸起区域，这防止在焊料回流期间非导电衬底的拐角处的焊料桥接。 还提供了具有这种焊料桥接防止结构的相应的半导体封装和半导体组件。

公开(公告)号：US09387613B2

公开(公告)日：2016-07-12

申请号：US14286282

申请日：2014-05-23

Applicant: Infineon Technologies AG

Inventor： Carlo Baterna Marbella ,  Ching Yun Tye ,  Ramasubramanian Natarajan

IPC: H01L23/495 ,  B29C45/27 ,  H01L23/31 ,  H01L21/56 ,  B29L31/34

CPC classification number: B29C45/2703 ,  B29L2031/3406 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/495 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A semiconductor package formation arrangement includes a mold housing with an interior cavity having top, bottom and first and second end sides. A gate for transferring liquefied molding material extends to the first end side. A lead frame having a top surface, a rear surface opposite the top surface and a mold flow modifier forms a first cavity section between the top surface and the top side and a second cavity section between the rear surface and the bottom side. A topology of the lead frame causes liquefied molding material to fill the first and second cavity sections at different rates. The mold flow modifier extends away from the lead frame so as to compensate for the difference between the first and second rates.

Abstract translation: 半导体封装形成装置包括具有内部空腔的模具壳体，其具有顶部，底部以及第一和第二端侧。 用于转移液化模塑材料的浇口延伸到第一端侧。 具有顶表面，与顶表面相对的后表面的引线框架和模流改性剂在顶表面和顶侧之间形成第一空腔部分，并且在后表面和底侧之间形成第二空腔部分。 引线框架的拓扑结构使得液化的模制材料以不同的速率填充第一和第二腔部分。 模具流动调节器远离引线框架延伸，以补偿第一和第二速率之间的差异。

公开(公告)号：US20150336314A1

公开(公告)日：2015-11-26

申请号：US14286282

申请日：2014-05-23

Applicant: Infineon Technologies AG

Inventor： Carlo Baterna Marbella ,  Ching Yun Tye ,  Ramasubramanian Natarajan

IPC: B29C45/27 ,  H01L23/31 ,  H01L21/56 ,  H01L23/495

CPC classification number: B29C45/2703 ,  B29L2031/3406 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/495 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A semiconductor package formation arrangement includes a mold housing with an interior cavity having top, bottom and first and second end sides. A gate for transferring liquefied molding material extends to the first end side. A lead frame having a top surface, a rear surface opposite the top surface and a mold flow modifier forms a first cavity section between the top surface and the top side and a second cavity section between the rear surface and the bottom side. A topology of the lead frame causes liquefied molding material to fill the first and second cavity sections at different rates. The mold flow modifier extends away from the lead frame so as to compensate for the difference between the first and second rates.

Abstract translation: 半导体封装形成装置包括具有内部空腔的模具壳体，其具有顶部，底部以及第一和第二端侧。 用于转移液化模塑材料的浇口延伸到第一端侧。 具有顶表面，与顶表面相对的后表面的引线框架和模流改性剂在顶表面和顶侧之间形成第一空腔部分，并且在后表面和底侧之间形成第二空腔部分。 引线框架的拓扑结构使得液化的模制材料以不同的速率填充第一和第二腔部分。 模具流动调节器远离引线框架延伸，以补偿第一和第二速率之间的差异。

公开(公告)号：US10085353B2

公开(公告)日：2018-09-25

申请号：US14077642

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Carlo Baterna Marbella ,  Fabian Schnoy

IPC: H05K7/10 ,  H05K7/12 ,  H05K3/34 ,  H05K1/11

CPC classification number: H05K3/3452 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09045 ,  H05K2201/09909 ,  H05K2201/10734

Abstract: A board for mechanically supporting and electrically connecting electronic components includes a non-conductive substrate, a plurality of electrically conductive traces and pads disposed on the non-conductive substrate, and a solder mask applied to the non-conductive substrate and covering the traces. Metal lines are disposed on the non-conductive substrate under the solder mask and along at least two sides of the pads disposed in corners of the non-conductive substrate, so that a metal line is interposed between the pads in the corners of the non-conductive substrate and each adjacent pad. The metal lines form a raised region in the solder mask along the metal lines which prevents solder bridging in the corners of the non-conductive substrate during solder reflow. A corresponding semiconductor package and semiconductor assembly with such solder bridging prevention structures are also provided.

公开(公告)号：US20160141187A1

公开(公告)日：2016-05-19

申请号：US14541163

申请日：2014-11-14

Applicant: Infineon Technologies AG

Inventor： Carlo Baterna Marbella ,  Wai Loon Kwan ,  Min King Chai ,  Veng Leong Tham

IPC: H01L21/56 ,  H01L23/42 ,  B29C51/26 ,  G07C11/00 ,  B29C51/12 ,  H01L23/31 ,  H01L21/67

CPC classification number: H01L21/565 ,  B29C51/12 ,  B29C51/264 ,  B29K2101/00 ,  B29L2031/3481 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: According to various embodiments, a method of manufacturing an integrated circuit may include providing a film structure having at least one of at least one recess or at least one protrusion, and carrying out a film assisted molding process using the film structure to mold an electronic circuit, thereby forming a molding structure including a surface pattern in accordance with the film structure.

Abstract translation: 根据各种实施例，制造集成电路的方法可以包括提供具有至少一个凹部或至少一个突起中的至少一个的薄膜结构，并且使用该薄膜结构来执行薄膜辅助模制工艺来模制电子电路 从而形成包括根据膜结构的表面图案的模制结构。

公开(公告)号：US09082737B2

公开(公告)日：2015-07-14

申请号：US13678421

申请日：2012-11-15

Applicant: Infineon Technologies AG

Inventor： Carlo Baterna Marbella ,  Ganesh Vetrivel Periasamy ,  Woon Yik Yong ,  Kok Kiat Koo ,  Christian Arndt ,  Edward Myers

IPC: H01L23/34 ,  H01L23/495 ,  H01L25/16 ,  H01L23/31

CPC classification number: H01L23/34 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49555 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract translation: 公开了一种包括故障打开机构的半导体封装。 一个实施例包括具有芯片载体的半导体封装，设置在芯片载体上的芯片和封装芯片和芯片载体的密封剂。 所述半导体封装还包括从所述密封剂突出的销和设置在所述密封剂上并连接到所述销的故障开放机构，其中所述故障开启机构被配置为如果温度超过预定温度则与所述销断开。

公开(公告)号：US20140131844A1

公开(公告)日：2014-05-15

申请号：US13678421

申请日：2012-11-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Carlo Baterna Marbella ,  Ganesh Vetrivel Periasamy ,  Woon Yik Yong ,  Kok Kiat Koo ,  Christian Arndt ,  Edward Myers

IPC: H01L23/34 ,  H01L23/495

CPC classification number: H01L23/34 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49555 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract translation: 公开了一种包括故障打开机构的半导体封装。 一个实施例包括具有芯片载体的半导体封装，设置在芯片载体上的芯片和封装芯片和芯片载体的密封剂。 所述半导体封装还包括从所述密封剂突出的销和设置在所述密封剂上并连接到所述销的故障开放机构，其中所述故障开启机构被配置为如果温度超过预定温度则与所述销断开。