公开(公告)号：US10312159B2

公开(公告)日：2019-06-04

申请号：US15798972

申请日：2017-10-31

Applicant: Infineon Technologies AG

Inventor： Frank Hoffmann ,  Dirk Manger ,  Andreas Pribil ,  Marc Probst ,  Stefan Tegen

IPC: H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/737

Abstract: A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.

公开(公告)号：US10748807B2

公开(公告)日：2020-08-18

申请号：US16293795

申请日：2019-03-06

Applicant: Infineon Technologies AG

Inventor： Torsten Helm ,  Marc Probst ,  Uwe Rudolph

IPC: H01L23/535 ,  H01L21/74 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor body having a main surface and a rear surface opposite the main surface, and a trench that extends from the main surface of the semiconductor body towards the rear surface, the trench having an upper trench portion and a lower trench portion, the trench having a width measured along a plane parallel to the main surface. The upper trench portion includes curved sidewalls that that bow outward from a bottom of the upper trench portion. The lower trench portion includes generally planar sidewalls that extend from bottom of the upper trench portion at a first depth into the semiconductor body along the first direction to a contact region. An electrically conductive contact electrode is within the trench, is electrically insulated from the semiconductor body along sidewalls of the trench, and electrically connects to the semiconductor body at a bottom of the trench.

公开(公告)号：US20190198380A1

公开(公告)日：2019-06-27

申请号：US16293795

申请日：2019-03-06

Applicant: Infineon Technologies AG

Inventor： Torsten Helm ,  Marc Probst ,  Uwe Rudolph

IPC: H01L21/74 ,  H01L23/535

CPC classification number: H01L21/743 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor body having a main surface and a rear surface opposite the main surface, and a trench that extends from the main surface of the semiconductor body towards the rear surface, the trench having an upper trench portion and a lower trench portion, the trench having a width measured along a plane parallel to the main surface. The upper trench portion includes curved sidewalls that that bow outward from a bottom of the upper trench portion. The lower trench portion includes generally planar sidewalls that extend from bottom of the upper trench portion at a first depth into the semiconductor body along the first direction to a contact region. An electrically conductive contact electrode is within the trench, is electrically insulated from the semiconductor body along sidewalls of the trench, and electrically connects to the semiconductor body at a bottom of the trench.

公开(公告)号：US20240213343A1

公开(公告)日：2024-06-27

申请号：US18533872

申请日：2023-12-08

Applicant: Infineon Technologies AG

Inventor： Roland Dietmüller ,  Andreas Korzenietz ,  Bernd Bitnar ,  Wolfgang Wagner ,  Philip Christoph Brandt ,  Frank Hille ,  Volodymyr Komarnitskyy ,  Frank Pfirsch ,  Franz Josef Niedernostheide ,  Marc Probst

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/42364 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A power semiconductor device includes a first region in an active region of a semiconductor body and including first trenches each having a first trench electrode electrically connected to a gate terminal and a first trench insulator. A second region includes second trenches each having a second trench electrode electrically connected to the gate terminal and a second trench insulator. At least one of the following applies: a minimal thickness of each second trench insulator amounts to at least 120% of a corresponding minimal thickness of each first trench insulator; an average thickness of the second trench insulators amounts to at least 120% of an average thickness of the first trench insulators; a trench bottom thickness of each second trench insulator amounts to at least 120% of a corresponding trench bottom thickness of each first trench insulator; a minimal breakdown voltage of each second trench insulator amounts to at least 120% of a minimal breakdown voltage of each first trench insulator.

公开(公告)号：US10262889B2

公开(公告)日：2019-04-16

申请号：US15602245

申请日：2017-05-23

Applicant: Infineon Technologies AG

Inventor： Torsten Helm ,  Marc Probst ,  Uwe Rudolph

IPC: H01L21/00 ,  H01L21/74 ,  H01L23/535

Abstract: An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.

公开(公告)号：US09812369B2

公开(公告)日：2017-11-07

申请号：US15083774

申请日：2016-03-29

Applicant: Infineon Technologies AG

Inventor： Frank Hoffmann ,  Dirk Manger ,  Andreas Pribil ,  Marc Probst ,  Stefan Tegen

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.

公开(公告)号：US20170256437A1

公开(公告)日：2017-09-07

申请号：US15602245

申请日：2017-05-23

Applicant: Infineon Technologies AG

Inventor： Torstern Helm ,  Marc Probst ,  Uwe Rudolph

IPC: H01L21/74 ,  H01L23/535

CPC classification number: H01L21/743 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.