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    Integrated circuit and method of forming an integrated circuit
    1.
    发明授权
    Integrated circuit and method of forming an integrated circuit 有权

    公开(公告)号：US10262889B2

    公开(公告)日：2019-04-16

    申请号：US15602245

    申请日：2017-05-23

    Applicant: Infineon Technologies AG

    Inventor： Torsten Helm ,  Marc Probst ,  Uwe Rudolph

    IPC: H01L21/00 ,  H01L21/74 ,  H01L23/535

    Abstract: An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.

    Integrated Circuit and Method of Forming an Integrated Circuit
    3.
    发明申请
    Integrated Circuit and Method of Forming an Integrated Circuit 审中-公开

    公开(公告)号：US20170256437A1

    公开(公告)日：2017-09-07

    申请号：US15602245

    申请日：2017-05-23

    Applicant: Infineon Technologies AG

    Inventor： Torstern Helm ,  Marc Probst ,  Uwe Rudolph

    IPC: H01L21/74 ,  H01L23/535

    CPC classification number: H01L21/743 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.

    METHOD FOR MANUFACTURING A PLURALITY OF NANOWIRES
    4.
    发明申请
    METHOD FOR MANUFACTURING A PLURALITY OF NANOWIRES 审中-公开
    制造多种纳米尺寸的方法

    公开(公告)号：US20160111719A1

    公开(公告)日：2016-04-21

    申请号：US14977719

    申请日：2015-12-22

    Applicant: Infineon Technologies AG

    Inventor： Marko Lemke ,  Stefan Tegen ,  Uwe Rudolph

    IPC: H01M4/38 ,  H01M4/66 ,  H01M10/0525 ,  H01L29/06 ,  H01L29/16

    Abstract: A method for manufacturing a plurality of nanowires, the method including: providing a carrier comprising an exposed surface of a material to be processed and applying a plasma treatment on the exposed surface of the material to be processed to thereby form a plurality of nanowires from the material to be processed during the plasma treatment.

    Abstract translation: 一种用于制造多个纳米线的方法，所述方法包括：提供包括待处理材料的暴露表面的载体，并在待处理材料的暴露表面上施加等离子体处理，从而形成多个纳米线 在等离子体处理期间待处理的材料。

    Integrated circuit and method of forming an integrated circuit
    7.
    发明授权
    Integrated circuit and method of forming an integrated circuit 有权

    公开(公告)号：US10748807B2

    公开(公告)日：2020-08-18

    申请号：US16293795

    申请日：2019-03-06

    Applicant: Infineon Technologies AG

    Inventor： Torsten Helm ,  Marc Probst ,  Uwe Rudolph

    IPC: H01L23/535 ,  H01L21/74 ,  H01L29/06

    Abstract: A semiconductor device includes a semiconductor body having a main surface and a rear surface opposite the main surface, and a trench that extends from the main surface of the semiconductor body towards the rear surface, the trench having an upper trench portion and a lower trench portion, the trench having a width measured along a plane parallel to the main surface. The upper trench portion includes curved sidewalls that that bow outward from a bottom of the upper trench portion. The lower trench portion includes generally planar sidewalls that extend from bottom of the upper trench portion at a first depth into the semiconductor body along the first direction to a contact region. An electrically conductive contact electrode is within the trench, is electrically insulated from the semiconductor body along sidewalls of the trench, and electrically connects to the semiconductor body at a bottom of the trench.

    Integrated Circuit and Method of Forming an Integrated Circuit
    10.
    发明申请
    Integrated Circuit and Method of Forming an Integrated Circuit 审中-公开

    公开(公告)号：US20190198380A1

    公开(公告)日：2019-06-27

    申请号：US16293795

    申请日：2019-03-06

    Applicant: Infineon Technologies AG

    Inventor： Torsten Helm ,  Marc Probst ,  Uwe Rudolph

    IPC: H01L21/74 ,  H01L23/535

    CPC classification number: H01L21/743 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor body having a main surface and a rear surface opposite the main surface, and a trench that extends from the main surface of the semiconductor body towards the rear surface, the trench having an upper trench portion and a lower trench portion, the trench having a width measured along a plane parallel to the main surface. The upper trench portion includes curved sidewalls that that bow outward from a bottom of the upper trench portion. The lower trench portion includes generally planar sidewalls that extend from bottom of the upper trench portion at a first depth into the semiconductor body along the first direction to a contact region. An electrically conductive contact electrode is within the trench, is electrically insulated from the semiconductor body along sidewalls of the trench, and electrically connects to the semiconductor body at a bottom of the trench.

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