公开(公告)号：US10284205B2

公开(公告)日：2019-05-07

申请号：US15331098

申请日：2016-10-21

Applicant: Infineon Technologies AG

Inventor： Samaksh Sinha ,  Sai Siddharth Pothapragada

IPC: H03L1/00 ,  H02M3/07 ,  H03L7/093 ,  H03L7/099 ,  H03L7/097 ,  H03L7/107

Abstract: A clock generator and a method to control an associated system are described. The clock generator (e.g., a PLL) can include a charge pump that can generate a current, and a controller coupled to the charge pump. The controller can determine a characteristic impacting operation of the clock generator and control the charge pump to adjust the current based on the determined characteristic to adjust a bandwidth of the clock generator. The clock generator and method can include adjusting the bandwidth to compensate for variations (e.g. PVT variations) that impact the operation of the clock generator to maintain constant or substantially constant bandwidth independent of such variations.

公开(公告)号：US20180115315A1

公开(公告)日：2018-04-26

申请号：US15331098

申请日：2016-10-21

Applicant: Infineon Technologies AG

Inventor： Samaksh Sinha ,  Sai Siddharth Pothapragada

IPC: H03L1/00 ,  H03L7/099 ,  H03L7/093 ,  H02M3/07

CPC classification number: H03L1/00 ,  H02M3/07 ,  H03L7/093 ,  H03L7/097 ,  H03L7/099 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/1075 ,  H03L2207/06

Abstract: A clock generator and a method to control an associated system are described. The clock generator (e.g., a PLL) can include a charge pump that can generate a current, and a controller coupled to the charge pump. The controller can determine a characteristic impacting operation of the clock generator and control the charge pump to adjust the current based on the determined characteristic to adjust a bandwidth of the clock generator. The clock generator and method can include adjusting the bandwidth to compensate for variations (e.g. PVT variations) that impact the operation of the clock generator to maintain constant or substantially constant bandwidth independent of such variations.

公开(公告)号：US09496888B1

公开(公告)日：2016-11-15

申请号：US14568239

申请日：2014-12-12

Applicant: Infineon Technologies AG

Inventor： Sunny Sharma ,  Chin Yeong Koh ,  Samaksh Sinha

IPC: H03M1/34 ,  H03M1/38 ,  H03M1/12 ,  H03M1/80 ,  H03M1/06 ,  H03M1/00

CPC classification number: H03M1/38 ,  H03M1/00 ,  H03M1/0692 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/125 ,  H03M1/468 ,  H03M1/804

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant binary scaled capacitance arrangement using a successive approximation technique can provide a fast and power efficient ADC, with improved error correction. For example, a successive approximation capacitor arrangement may include multiple arrays of capacitances with binary bit weights. In an implementation, the technique includes processing the capacitances in successive cycles, where each cycle generates a binary error correction code representing greater than one bit of the digital output.

Abstract translation: 设备和技术的代表性实现提供时分离模拟输入的模数转换。 使用逐次逼近技术的冗余二进制缩放电容布置可以提供快速和功率效率的ADC，具有改进的纠错。 例如，逐次逼近电容器布置可以包括具有二进制位权重的多个电容阵列。 在一个实现中，该技术包括在连续周期中处理电容，其中每个周期产生代表数字输出的大于1位的二进制纠错码。