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公开(公告)号：US11177987B1
公开(公告)日：2021-11-16
申请号：US17081433
申请日：2020-10-27
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , Michael Augustin , Ketan Dewan , Ralph Mueller-Eschenbach , Juergen Schaefer
Abstract: Processing a resolver signal by a microcontroller includes generating, by a carrier signal generator, a carrier signal for output to a resolver; receiving modulated carrier signals from a resolver via hardware that is external to the microcontroller; integrating, by an integrator, respective integrator input signals which are based on the modulated carrier signals, to generate respective envelope signals, wherein a start of an integration window of the integrator is set with respect to a start of the carrier signal; and determining an angular position sensed by the resolver based on the envelope signals.
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2.发明授权公开(公告)号：US10816642B2
公开(公告)日：2020-10-27
申请号：US16011657
申请日：2018-06-19
Applicant: Infineon Technologies AG
Inventor： Ketan Dewan , Reinhard Kussian , Juergen Schaefer
IPC: G01S7/282 , G01S7/03 , G01S13/931
Abstract: In various embodiments, a circuitry configured to generate a voltage is provided. The circuitry may include a sequence generator configured to provide a sequence of data words consisting of bits. The number of bits is greater than two. The circuitry may further include a delta-sigma modulator configured to receive the sequence of data words provided by the sequence generator and to provide a delta-sigma modulated first single bit data stream at a first data rate, and a decimation filter configured to generate a stream of decimated data words from the first single bit data stream at a second data rate. The second data rate may be smaller than the first data rate, each decimated data word including a plurality of bits. The circuitry may further include a parallel-to-serial converter configured to convert the decimated data words to a second single bit data stream while preserving the second data rate.
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公开(公告)号：US20190068214A1
公开(公告)日：2019-02-28
申请号：US15690728
申请日：2017-08-30
Applicant: Infineon Technologies AG
Inventor： Ketan Dewan , Reinhard Kussian , Juergen Schaefer
IPC: H03M3/00
Abstract: A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.
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公开(公告)号：US12056253B2
公开(公告)日：2024-08-06
申请号：US17340761
申请日：2021-06-07
Applicant: Infineon Technologies AG
Inventor： Ketan Dewan , Trevor Bird , Simon Cottam , Glenn Ashley Farrall , Darren Galpin , Frank Hellwig , Paul Hubbert , Dietmar Koenig , Shubhendu Mahajan , Sandeep Vangipuram
CPC classification number: G06F21/6218 , G06F21/85 , H03M13/09
Abstract: An interconnect including an input couplable to a source, and an encoder coupled to the input. The encoder is configured to: group information that is received from the source via a same channel; size the grouped information to a common width; and apply protection to the sized grouped information.
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公开(公告)号：US11881861B2
公开(公告)日：2024-01-23
申请号：US17584836
申请日：2022-01-26
Applicant: Infineon Technologies AG
Inventor： Sunanda Manjunath , Ketan Dewan , Juergen Schaefer
IPC: H03K5/1534 , H03K5/08 , H03K7/08 , H03K19/17736 , H03K5/05 , H03K5/00
CPC classification number: H03K5/1534 , H03K5/05 , H03K5/086 , H03K7/08 , H03K19/17744 , H03K2005/00136
Abstract: Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.
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Patent Agency Ranking
公开(公告)号：US11668763B2
公开(公告)日：2023-06-06
申请号：US17739347
申请日：2022-05-09
Applicant: Infineon Technologies AG
Inventor： Ketan Dewan , Rocco Calabro , Juergen Schaefer
Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.
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公开(公告)号：US11614485B2
公开(公告)日：2023-03-28
申请号：US17318168
申请日：2021-05-12
Applicant: Infineon Technologies AG
Inventor： Michael Augustin , Ketan Dewan
IPC: G01R31/3177 , H03M3/00 , H04L43/16 , G01R31/00 , G01R31/08 , H04L1/24 , G06F119/10
Abstract: A safety mechanism device includes measuring whether a first output signal or results meets dynamically adjustable boundary criterion. The safety mechanism compares the first output signal with at least one boundary signal that is dynamically adjusted. The safety mechanism can produce a dynamically or automatically adjusted boundary signal using a second output signal. The second output signal can mimic the first output signal.
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公开(公告)号：US11705917B2
公开(公告)日：2023-07-18
申请号：US17467767
申请日：2021-09-07
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , Ketan Dewan , Rex Kho , Ralph Mueller-Eschenbach , Juergen Schaefer
IPC: H03M1/12 , G01R31/317 , G06F1/10
CPC classification number: H03M1/1245 , G01R31/31709 , G06F1/10
Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.
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公开(公告)号：US10523190B2
公开(公告)日：2019-12-31
申请号：US15824345
申请日：2017-11-28
Applicant: Infineon Technologies AG
Inventor： Pedro Costa , Ketan Dewan
Abstract: A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.
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公开(公告)号：US20190165775A1
公开(公告)日：2019-05-30
申请号：US15824345
申请日：2017-11-28
Applicant: Infineon Technologies AG
Inventor： Pedro Costa , Ketan Dewan
Abstract: A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.
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