公开(公告)号：US20240356721A1

公开(公告)日：2024-10-24

申请号：US18631133

申请日：2024-04-10

Applicant: Infineon Technologies AG

Inventor： Sunanda Manjunath ,  Christian Müller

IPC: H04L7/00

CPC classification number: H04L7/0012

Abstract: An electronic device including a master device, the master device including an interface component to a slave device. The interface component includes a sampling circuit having a clock input, a transmit clock generator configured to generate a transmit clock, a first off-chip driver configured to receive the transmit clock and provide the transmit clock to the slave device, a second off-chip driver configured to receive the transmit clock and configured to supply the transmit clock to the clock input of the sampling circuit of the interface component and a data input configured to receive data from the slave device. The sampling circuit is configured to sample the received data in accordance with the transmit clock supplied by the second off-chip driver.

公开(公告)号：US20230238949A1

公开(公告)日：2023-07-27

申请号：US17584836

申请日：2022-01-26

Applicant: Infineon Technologies AG

Inventor： Sunanda Manjunath ,  Ketan Dewan ,  Juergen Schaefer

IPC: H03K5/1534 ,  H03K5/08 ,  H03K5/05 ,  H03K7/08 ,  H03K19/17736

CPC classification number: H03K5/1534 ,  H03K5/086 ,  H03K5/05 ,  H03K7/08 ,  H03K19/17744 ,  H03K2005/00136

Abstract: Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.

公开(公告)号：US20230123080A1

公开(公告)日：2023-04-20

申请号：US17502300

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Sunanda Manjunath ,  Jens Rosenbusch

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/16

Abstract: Systems, methods, and circuitries are provided for checking integrity of code received from an external memory. In one example, a system includes a non-volatile memory and a controller. The non-volatile memory includes a first partition configured to store first data corresponding to program code and a second partition configured to store second data corresponding to a copy of the first data. The controller that includes a processor and comparator circuitry. The comparator circuitry is configured to receive a portion of the first data and a corresponding portion of the second data, compare the portion of the first data to the portion of the second data, when the portion of the first data matches the portion of the second data, provide the portion of the first data to the processor, and when the portion of the first data does not match the portion of the second data, generate an alarm signal.

公开(公告)号：US11881861B2

公开(公告)日：2024-01-23

申请号：US17584836

申请日：2022-01-26

Applicant: Infineon Technologies AG

Inventor： Sunanda Manjunath ,  Ketan Dewan ,  Juergen Schaefer

IPC: H03K5/1534 ,  H03K5/08 ,  H03K7/08 ,  H03K19/17736 ,  H03K5/05 ,  H03K5/00

CPC classification number: H03K5/1534 ,  H03K5/05 ,  H03K5/086 ,  H03K7/08 ,  H03K19/17744 ,  H03K2005/00136

Abstract: Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.

公开(公告)号：US11640332B1

公开(公告)日：2023-05-02

申请号：US17502300

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Sunanda Manjunath ,  Jens Rosenbusch

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/07

Abstract: Systems, methods, and circuitries are provided for checking integrity of code received from an external memory. In one example, a system includes a non-volatile memory and a controller. The non-volatile memory includes a first partition configured to store first data corresponding to program code and a second partition configured to store second data corresponding to a copy of the first data. The controller that includes a processor and comparator circuitry. The comparator circuitry is configured to receive a portion of the first data and a corresponding portion of the second data, compare the portion of the first data to the portion of the second data, when the portion of the first data matches the portion of the second data, provide the portion of the first data to the processor, and when the portion of the first data does not match the portion of the second data, generate an alarm signal.