公开(公告)号：US20160093728A1

公开(公告)日：2016-03-31

申请号：US14868857

申请日：2015-09-29

Applicant: Infineon Technologies AG

Inventor： Stefan Decker ,  Sven Lanzerstorfer ,  Thorsten Meyer ,  Robert Zink

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811

Abstract: A semiconductor device comprises a semiconductor body. The semiconductor body comprises insulated gate field effect transistor cells. At least one of the insulated gate field effect transistor cells comprises a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, a drift zone of the first conductivity type, and a trench gate structure extending into the semiconductor body through the body zone along a vertical direction. The trench gate structure comprises a gate electrode separated from the semiconductor body by a trench dielectric. The trench dielectric comprises a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone. The ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5.

Abstract translation: 半导体器件包括半导体本体。 半导体本体包括绝缘栅场效应晶体管单元。 绝缘栅场效应晶体管单元中的至少一个包括第一导电类型的源极区，第二互补导电类型的体区，第一导电类型的漂移区和延伸到半导体中的沟槽栅结构 身体通过身体区域沿垂直方向。 沟槽栅极结构包括通过沟槽电介质与半导体本体分离的栅电极。 沟槽电介质包括介于栅极电极和源极区之间的源极介电部分和介于栅极电极和主体区域之间的栅极电介质部分。 源电介质部分沿横向方向的最大厚度与栅电介质部分沿横向方向的最小厚度之比至少为1.5。

公开(公告)号：US09837530B2

公开(公告)日：2017-12-05

申请号：US14868857

申请日：2015-09-29

Applicant: Infineon Technologies AG

Inventor： Stefan Decker ,  Sven Lanzerstorfer ,  Thorsten Meyer ,  Robert Zink

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L29/739 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811

Abstract: A semiconductor device comprises a semiconductor body. The semiconductor body comprises insulated gate field effect transistor cells. At least one of the insulated gate field effect transistor cells comprises a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, a drift zone of the first conductivity type, and a trench gate structure extending into the semiconductor body through the body zone along a vertical direction. The trench gate structure comprises a gate electrode separated from the semiconductor body by a trench dielectric. The trench dielectric comprises a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone. The ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5.

公开(公告)号：US09570441B2

公开(公告)日：2017-02-14

申请号：US14745908

申请日：2015-06-22

Applicant: Infineon Technologies AG

Inventor： Yulia Kotsar ,  Sven Lanzerstorfer ,  Robert Zink

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32105 ,  H01L21/32155 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/0922 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: A first trench and a second trench, both extending from a main surface into a semiconductor layer, are filled with a first fill material. The first fill material is selectively recessed in the first trench. A mask is formed that covers the second trench and that exposes the first trench. An oxidation rate promoting material is implanted into an exposed first section of the recessed fill material in the first trench. The mask is removed. Then the first fill material is thermally oxidized, wherein on the first section an oxidation rate is at least twice as high as on non-implanted sections of the first fill material.

Abstract translation: 从主表面延伸到半导体层中的第一沟槽和第二沟槽都填充有第一填充材料。 第一填充材料选择性地凹入第一沟槽中。 形成覆盖第二沟槽并露出第一沟槽的掩模。 将氧化速率促进材料注入到第一沟槽中的凹陷填充材料的暴露的第一部分中。 去除面具。 然后第一填充材料被热氧化，其中在第一部分上的氧化速率是至少两倍于第一填充材料的非植入部分的高度。

公开(公告)号：US20150380403A1

公开(公告)日：2015-12-31

申请号：US14745908

申请日：2015-06-22

Applicant: Infineon Technologies AG

Inventor： Yulia Kotsar ,  Sven Lanzerstorfer ,  Robert Zink

IPC: H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32105 ,  H01L21/32155 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/0922 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: A first trench and a second trench, both extending from a main surface into a semiconductor layer, are filled with a first fill material. The first fill material is selectively recessed in the first trench. A mask is formed that covers the second trench and that exposes the first trench. An oxidation rate promoting material is implanted into an exposed first section of the recessed fill material in the first trench. The mask is removed. Then the first fill material is thermally oxidized, wherein on the first section an oxidation rate is at least twice as high as on non-implanted sections of the first fill material.

Abstract translation: 从主表面延伸到半导体层中的第一沟槽和第二沟槽都填充有第一填充材料。 第一填充材料选择性地凹入第一沟槽中。 形成覆盖第二沟槽并露出第一沟槽的掩模。 将氧化速率促进材料注入到第一沟槽中的凹陷填充材料的暴露的第一部分中。 去除面具。 然后第一填充材料被热氧化，其中在第一部分上的氧化速率是至少两倍于第一填充材料的非植入部分的高度。

公开(公告)号：US09590094B2

公开(公告)日：2017-03-07

申请号：US14738245

申请日：2015-06-12

Applicant: Infineon Technologies AG

Inventor： Robert Zink ,  Stefan Decker ,  Sven Lanzerstorfer

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/40 ,  H01L21/265 ,  H01L27/092

CPC classification number: H01L29/7811 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/76202 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66568 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7813

Abstract: By thermal oxidation a field oxide layer is formed that lines first and second trenches that extend from a main surface into a semiconductor layer. After the thermal oxidation, field electrodes and trench gate electrodes of power transistor cells are formed in the first and second trenches. A protection cover including a silicon nitride layer is formed that covers a cell area with the first and second trenches. With the protection cover covering the cell area, planar gate electrodes of lateral transistors are formed in a support area of the semiconductor layer.

Abstract translation: 通过热氧化形成场氧化物层，其形成从主表面延伸到半导体层中的第一和第二沟槽。 在热氧化之后，在第一和第二沟槽中形成功率晶体管单元的场电极和沟槽栅电极。 形成包括氮化硅层的保护盖，其覆盖具有第一和第二沟槽的单元区域。 通过覆盖单元区域的保护盖，横向晶体管的平面栅电极形成在半导体层的支撑区域中。

公开(公告)号：US20150380543A1

公开(公告)日：2015-12-31

申请号：US14738245

申请日：2015-06-12

Applicant: Infineon Technologies AG

Inventor： Robert Zink ,  Stefan Decker ,  Sven Lanzerstorfer

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/40 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/76202 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66568 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7813

Abstract: By thermal oxidation a field oxide layer is formed that lines first and second trenches that extend from a main surface into a semiconductor layer. After the thermal oxidation, field electrodes and trench gate electrodes of power transistor cells are formed in the first and second trenches. A protection cover including a silicon nitride layer is formed that covers a cell area with the first and second trenches. With the protection cover covering the cell area, planar gate electrodes of lateral transistors are formed in a support area of the semiconductor layer.

Abstract translation: 通过热氧化形成场氧化物层，其形成从主表面延伸到半导体层中的第一和第二沟槽。 在热氧化之后，在第一和第二沟槽中形成功率晶体管单元的场电极和沟槽栅电极。 形成包括氮化硅层的保护盖，其覆盖具有第一和第二沟槽的单元区域。 通过覆盖单元区域的保护盖，横向晶体管的平面栅电极形成在半导体层的支撑区域中。