公开(公告)号：US09558114B2

公开(公告)日：2017-01-31

申请号：US13908040

申请日：2013-06-03

Applicant: Infineon Technologies AG

Inventor： Rex Kho ,  Michael Hassel ,  Wolfgang Beck ,  Thomas Liebermann

IPC: G06F12/06 ,  G11C8/12 ,  G11C16/24

CPC classification number: G06F12/0646 ,  G11C8/12 ,  G11C16/24 ,  G11C2211/5641

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for storing data in an adjustably partitionable memory array, and a method to store data in an adjustably partitionable memory array. According to an embodiment of the disclosure, a system to store data in an adjustably partitionable memory array is provided, the system including a plurality of memory cells arranged in an array of rows and columns, a plurality of bit lines, and a plurality of switches, wherein each bit line is electrically coupled to a column of memory cells and each bit line comprises a switch configured to allow the respective bit line to be partitioned by opening of the switch.

Abstract translation: 本公开涉及一种电子存储器系统，更具体地，涉及一种用于将数据存储在可调节分区存储器阵列中的系统，以及一种将数据存储在可调节分割存储器阵列中的方法。 根据本公开的实施例，提供了一种将数据存储在可调节的可分区存储器阵列中的系统，所述系统包括以行和列排列的多个存储器单元，多个位线和多个开关 ，其中每个位线电耦合到存储器单元的列，并且每个位线包括被配置为允许通过打开所述开关来分隔相应位线的开关。

公开(公告)号：US20140359249A1

公开(公告)日：2014-12-04

申请号：US13908040

申请日：2013-06-03

Applicant: Infineon Technologies AG

Inventor： Rex Kho ,  Michael Hassel ,  Wolfgang Beck ,  Thomas Liebermann

IPC: G06F12/06

CPC classification number: G06F12/0646 ,  G11C8/12 ,  G11C16/24 ,  G11C2211/5641

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for storing data in an adjustably partitionable memory array, and a method to store data in an adjustably partitionable memory array. According to an embodiment of the disclosure, a system to store data in an adjustably partitionable memory array is provided, the system including a plurality of memory cells arranged in an array of rows and columns, a plurality of bit lines, and a plurality of switches, wherein each bit line is electrically coupled to a column of memory cells and each bit line comprises a switch configured to allow the respective bit line to be partitioned by opening of the switch.

Abstract translation: 本公开涉及一种电子存储器系统，更具体地，涉及一种用于将数据存储在可调节分区存储器阵列中的系统，以及一种将数据存储在可调节分割存储器阵列中的方法。 根据本公开的实施例，提供了一种将数据存储在可调节的可分区存储器阵列中的系统，所述系统包括以行和列排列的多个存储器单元，多个位线和多个开关 ，其中每个位线电耦合到存储器单元的列，并且每个位线包括被配置为允许通过打开所述开关来分隔相应位线的开关。

公开(公告)号：US09343179B2

公开(公告)日：2016-05-17

申请号：US14132053

申请日：2013-12-18

Applicant: Infineon Technologies AG

Inventor： Thomas Nirschl ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Kern ,  Thomas Liebermann

IPC: G11C29/00 ,  G11C29/02 ,  G06F11/10

CPC classification number: G11C29/024 ,  G06F11/1076

Abstract: A system and method for performing three scans for testing an address decoder and word line drive circuits is disclosed. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected.

Abstract translation: 公开了一种执行三次扫描以测试地址解码器和字线驱动电路的系统和方法。 第一次扫描确定是否只选择一个字线。 第二扫描确定到目标​​电压电平的字线上升时间是否在指定时间内。 最后，第三次扫描确定是否选择了正确的字线。

公开(公告)号：US20150170762A1

公开(公告)日：2015-06-18

申请号：US14132053

申请日：2013-12-18

Applicant: Infineon Technologies AG

Inventor： Thomas Nirschl ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Kern ,  Thomas Liebermann

IPC: G11C29/02 ,  G06F11/10

CPC classification number: G11C29/024 ,  G06F11/1076

Abstract: The disclosure relates to systems and methods for performing a word line address scan in a semiconductor memory. More specifically, the disclosure provides a system and method for performing three scans for testing address decoder and word line drive circuits. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected. The present disclosure may realize all three scans or a combination of the three scans.

Abstract translation: 本公开涉及用于在半导体存储器中执行字线地址扫描的系统和方法。 更具体地，本公开提供了一种用于对地址解码器和字线驱动电路进行三次扫描的系统和方法。 第一次扫描确定是否只选择一个字线。 第二扫描确定到目标​​电压电平的字线上升时间是否在指定时间内。 最后，第三次扫描确定是否选择了正确的字线。 本公开可以实现所有三个扫描或三个扫描的组合。