公开(公告)号：US20160308495A1

公开(公告)日：2016-10-20

申请号：US14689662

申请日：2015-04-17

Applicant: Infineon Technologies AG

Inventor： Tim Canning ,  Christian Schuberth ,  David Seebacher

IPC: H03F1/02 ,  H03F3/21 ,  H03F3/19

CPC classification number: H03F1/0288 ,  H03F3/602 ,  H03F2200/09 ,  H03F2200/451

Abstract: A Doherty amplifier circuit includes an RF input terminal, an RF output terminal, a main amplifier having a first input terminal and a first output driving terminal, and a peaking amplifier having a second input terminal and a second output driving terminal. An output combining network is configured to feed output current from the first and second output driving terminals into a summing node. The output combining network includes a transmission line transformer balun having first and second input ports and a first output port being connected to the summing node, a first electrical connection between the first output driving terminal and the first input port, and a second electrical connection between the second output driving terminal and the second input port. The second electrical connection includes a quarter wave impedance inverter. A first output impedance matching network is connected between the summing node and the RF output terminal.

Abstract translation: Doherty放大器电路包括RF输入端子，RF输出端子，具有第一输入端子和第一输出驱动端子的主放大器，以及具有第二输入端子和第二输出驱动端子的峰值放大器。 输出组合网络被配置为将来自第一和第二输出驱动终端的输出电流馈送到求和节点。 输出组合网络包括具有第一和第二输入端口的传输线变压器平衡 - 不平衡转换器和连接到求​​和节点的第一输出端口，第一输出驱动端子和第一输入端口之间的第一电连接， 第二输出驱动端子和第二输入端口。 第二电连接包括四分之一波阻抗逆变器。 第一输出阻抗匹配网络连接在求和节点和RF输出终端之间。

公开(公告)号：US10171039B2

公开(公告)日：2019-01-01

申请号：US14840963

申请日：2015-08-31

Applicant: Infineon Technologies AG

Inventor： David Seebacher ,  Christian Schuberth ,  Peter Singerl ,  Tim Canning ,  Richard Wilson ,  Haedong Jang

IPC: H03F3/68 ,  H03F1/02 ,  H03F1/56 ,  H03F3/193 ,  H03F3/21 ,  H03F3/72

Abstract: A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.

公开(公告)号：US20170063308A1

公开(公告)日：2017-03-02

申请号：US14840963

申请日：2015-08-31

Applicant: Infineon Technologies AG

Inventor： David Seebacher ,  Christian Schuberth ,  Peter Singerl ,  Tim Canning ,  Richard Wilson ,  Haedong Jang

IPC: H03F1/02 ,  H03F3/193 ,  H03F3/21 ,  H03F1/56

CPC classification number: H03F1/0277 ,  H03F1/0288 ,  H03F1/56 ,  H03F3/193 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/318 ,  H03F2200/451 ,  H03F2203/7233

Abstract: A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.

Abstract translation: 公开了一种峰值放大器。 峰值放大器包括驱动级，最后级和级间匹配网络。 驱动器级具有负载阻抗，并且被配置为基于输入信号产生驱动器输出。 最终阶段具有最终级输入阻抗，并且被配置为基于驱动器输出生成峰值输出。 阶段匹配网络耦合到驱动阶段和最后阶段。 阶段匹配网络被配置为当峰化放大器导通时将最终级输入阻抗转换为驱动级的负载阻抗，并且当峰化放大器处于关闭状态时，将最终级输入阻抗转换为最终级的输入。