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公开(公告)号：US10930990B2
公开(公告)日：2021-02-23
申请号：US16277398
申请日：2019-02-15
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Andrea Del Chiaro , Christian Schuberth , Peter Singerl , Ji Zhao
Abstract: A device includes at least one electrically conductive structure and at least one stripline. The stripline includes stripline sections that are connected to one another in a series connection between a first terminal and a second terminal. A first subset of the stripline sections is arranged on a first side of the conductive structure and a second subset of the stripline sections is arranged on a second side of the conductive structure. The device also includes at least one conductive connection between the first subset of the stripline sections and the second subset of the stripline sections, wherein the at least one conductive connection is isolated from the at least one electrically conductive structure.
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公开(公告)号：US10778156B2
公开(公告)日：2020-09-15
申请号：US15627880
申请日：2017-06-20
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Christian Schuberth , Peter Singerl , Ji Zhao
IPC: H03F3/68 , H03F1/56 , H01L23/00 , H01L23/66 , H01L25/07 , H01L29/20 , H01L29/778 , H01L29/78 , H03F1/02 , H03F3/195
Abstract: A circuit includes a first power transistor stage internally configured to function as a voltage-controlled current source, a second power transistor stage having an input impedance which varies as a function of input power and an interstage matching network coupling an output of the first power transistor stage to an input of the second power transistor stage. The interstage matching network is configured to provide impedance inversion between the input of the second power transistor stage and the output of the first power transistor stage. The impedance inversion provided by the interstage matching network transforms the first power transistor stage from functioning as a voltage-controlled current source to functioning as a voltage-controlled voltage source at the input of the second power transistor stage.
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公开(公告)号：US10741476B2
公开(公告)日：2020-08-11
申请号：US15490991
申请日：2017-04-19
Applicant: Infineon Technologies AG
Inventor： Christian Schuberth , David Seebacher
IPC: H01L29/00 , H01L23/48 , H01L49/02 , H01L23/367 , H01L23/522 , H01L23/36 , H01L23/66 , H01L23/498
Abstract: A passive electrical component includes a substrate. A first metallization layer is formed on the substrate. A first dielectric layer is formed on the first metallization layer The first dielectric layer has a lower thermal conductivity than the substrate. A second metallization layer is formed on the first dielectric layer. An electrically conductive via provides an electrical connection between a first section of the first metallization layer and a second section of the second metallization layer. A thermally conductive via provides a thermally conductive path between the second section and the substrate. The thermally conductive via provides an open circuit termination to the second section of the second metallization layer.
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公开(公告)号：US10727793B2
公开(公告)日：2020-07-28
申请号：US16106796
申请日：2018-08-21
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Pantelis Sarais , Peter Singerl , Herwig Wappis
IPC: H04B1/04 , H03F3/24 , H03F1/02 , H04B1/401 , H03F3/193 , H03F3/19 , H03F3/45 , H04B1/38 , H04J3/02
Abstract: Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.
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公开(公告)号：US09882535B2
公开(公告)日：2018-01-30
申请号：US15195575
申请日：2016-06-28
Applicant: Infineon Technologies AG
Inventor： Haedong Jang , Richard Wilson , Timothy Canning , David Seebacher
CPC classification number: H03F1/0288 , H03F1/0294 , H03F1/56 , H03F3/193 , H03F3/245 , H03F3/604 , H03F2200/255 , H03F2200/423 , H03F2200/451
Abstract: An amplifier that is configured to amplify an RF signal includes a power combiner circuit. The power combiner circuit includes a first branch connected between a first RF input port and a summing node and a second branch connected between a second RF input port and the summing node. Each of the first and second branches includes an impedance inverter. The Chireix combiner is configured to present a Chireix load modulated impedance response to the first and second RF input ports. The power combiner circuit further includes compensation elements being configured to at least partially compensate for a reactance of the Chireix combiner circuit in a Doherty amplifier mode in which a signal is applied to the first RF input port and the second RF input port is electrically open.
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Patent Agency Ranking
公开(公告)号：US20150130549A1
公开(公告)日：2015-05-14
申请号：US14079923
申请日：2013-11-14
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Peter Singerl , Christian Schuberth , Martin Mataln
IPC: H03K7/08
CPC classification number: H03K7/08
Abstract: A method for providing cross point information includes: providing an input signal having amplitude and phase information; interpolating between a first point of the input signal and a second point of the input signal to provide cross point information between the first point and the second point; and providing a pulse-width modulated signal based on the input signal and the cross point information.
Abstract translation: 提供交叉点信息的方法包括：提供具有振幅和相位信息的输入信号; 在所述输入信号的第一点和所述输入信号的第二点之间进行内插以在所述第一点和所述第二点之间提供交叉点信息; 以及基于输入信号和交叉点信息提供脉冲宽度调制信号。
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公开(公告)号：US11831279B2
公开(公告)日：2023-11-28
申请号：US17227755
申请日：2021-04-12
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Matteo Bassi , Dmytro Cherniak , Fabio Padovan
CPC classification number: H03F1/0205 , H03F3/245 , H03F2200/294 , H03F2200/451
Abstract: In accordance with an embodiment, a method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor includes: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.
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公开(公告)号：US20190058448A1
公开(公告)日：2019-02-21
申请号：US16106796
申请日：2018-08-21
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Pantelis Sarais , Peter Singerl , Herwig Wappis
Abstract: Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.
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公开(公告)号：US10171039B2
公开(公告)日：2019-01-01
申请号：US14840963
申请日：2015-08-31
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Christian Schuberth , Peter Singerl , Tim Canning , Richard Wilson , Haedong Jang
Abstract: A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.
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公开(公告)号：US20180308919A1
公开(公告)日：2018-10-25
申请号：US15490991
申请日：2017-04-19
Applicant: Infineon Technologies AG
Inventor： Christian Schuberth , David Seebacher
IPC: H01L49/02 , H01L23/367 , H01L23/373 , H01L23/522
Abstract: A passive electrical component includes a substrate. A first metallization layer is formed on the substrate. A first dielectric layer is formed on the first metallization layer The first dielectric layer has a lower thermal conductivity than the substrate. A second metallization layer is formed on the first dielectric layer. An electrically conductive via provides an electrical connection between a first section of the first metallization layer and a second section of the second metallization layer. A thermally conductive via provides a thermally conductive path between the second section and the substrate. The thermally conductive via provides an open circuit termination to the second section of the second metallization layer.
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