-
公开(公告)号：US11411500B2
公开(公告)日：2022-08-09
申请号：US16680957
申请日：2019-11-12
Applicant: Infineon Technologies Austria AG
Inventor： Mattia Oddicini , Kelsey Curtis , Tim Ng , Cha-Fu Tsai
Abstract: A controller for a power converter includes: a first sense terminal and a second sense terminal for sensing an output voltage of the power converter; a bridging circuit configured to electrically couple the first sense terminal to the second sense terminal in a first state and electrically decouple the first sense terminal from the second sense terminal in a second state; and control circuitry configured to set the bridging circuit in the first state during a portion of a voltage ramp of the power converter, and to determine whether an open or short fault condition is present at either the first sense terminal or the second sense terminal based on a voltage across the bridging circuit in the first state.
-
公开(公告)号：US10481626B1
公开(公告)日：2019-11-19
申请号：US16107528
申请日：2018-08-21
Applicant: Infineon Technologies Austria AG
Inventor： Benjamim Tang , Jinghong Guo , Harrison Hu , Tim Ng , Mattia Oddicini , Herbert Zojer
Abstract: A fault-tolerant multiphase voltage regulator includes a plurality of power stages, each of which is configured to deliver a phase current to a processor, and a controller. The controller is configured to: control the plurality of power stages to regulate an output voltage provided to the processor; detect and disable a faulty power stage; generate a throttling signal to indicate if one or more of the power stages is faulty and disabled; and communicate the throttling signal to the processor over a physical line running between the processor and the controller. A corresponding method of operating a fault-tolerant power distribution system is also described.
-
公开(公告)号：US11444632B2
公开(公告)日：2022-09-13
申请号：US17077475
申请日：2020-10-22
Applicant: Infineon Technologies Austria AG
Inventor： Sujata Sen , Mattia Oddicini , Luca Petruzzi , Benjamim Tang
Abstract: A tracking analog-to-digital converter (ADC) for a power converter includes a first tracking loop and a second tracking loop. The first tracking loop is configured to track a voltage input to the tracking ADC using one or more comparators and has a re-clocking circuit to mitigate the impact of comparator output metastability, but introduces multi-cycle latency which increases a residual error of the voltage tracking provided by the first tracking loop. The second tracking loop is configured to supplement the voltage tracking provided by the first tracking loop and to reduce the residual error of the voltage tracking for dynamic changes at the voltage input. The second tracking loop has a single-cycle latency and is implemented with logic that is less sensitive to logic errors due to comparator metastability. Corresponding methods of voltage tracking and an electronic system are also described.
-
公开(公告)号：US11070125B2
公开(公告)日：2021-07-20
申请号：US16666884
申请日：2019-10-29
Applicant: Infineon Technologies Austria AG
Inventor： Benjamim Tang , Jinghong Guo , Harrison Hu , Tim Ng , Mattia Oddicini , Herbert Zojer
Abstract: A fault-tolerant multiphase voltage regulator includes a plurality of power stages, each of which is configured to deliver a phase current to a processor, and a controller. The controller is configured to: control the plurality of power stages to regulate an output voltage provided to the processor; detect and disable a faulty power stage; generate a throttling signal to indicate that one or more of the power stages is faulty and disabled; communicate the throttling signal to the processor over a physical line running between the processor and the controller; and place the multiphase voltage regulator in a self-test mode in which the processor is operated at a known computational load and the controller operates each power stage independently to determine if any of the power stages is faulty under the known computational load. A corresponding method of operating a fault-tolerant power distribution system is also described.
-
公开(公告)号：US20210143740A1
公开(公告)日：2021-05-13
申请号：US16680957
申请日：2019-11-12
Applicant: Infineon Technologies Austria AG
Inventor： Mattia Oddicini , Kelsey Curtis , Tim Ng , Cha-Fu Tsai
Abstract: A controller for a power converter includes: a first sense terminal and a second sense terminal for sensing an output voltage of the power converter; a bridging circuit configured to electrically couple the first sense terminal to the second sense terminal in a first state and electrically decouple the first sense terminal from the second sense terminal in a second state; and control circuitry configured to set the bridging circuit in the first state during a portion of a voltage ramp of the power converter, and to determine whether an open or short fault condition is present at either the first sense terminal or the second sense terminal based on a voltage across the bridging circuit in the first state.
-
Patent Agency Ranking
公开(公告)号：US09882481B2
公开(公告)日：2018-01-30
申请号：US15200882
申请日：2016-07-01
Applicant: Infineon Technologies Austria AG
Inventor： Matthew Mascioli , Mattia Oddicini , Herbert Zojer
CPC classification number: H02M3/158 , H02M1/36 , H02M2001/0025
Abstract: A method of regulating an output voltage of a buck converter during a startup period in which the buck converter is first enabled includes regulating the output voltage of the buck converter to a reference voltage under current-mode control during a first part of the startup period, and regulating the output voltage of the buck converter to the reference voltage under voltage-mode control during a second, later part of the startup period. The reference voltage ramps up from an initial voltage at the beginning of the startup period to a target voltage at the end of the startup period. Buck converter embodiments are also described.
-
公开(公告)号：US20180006560A1
公开(公告)日：2018-01-04
申请号：US15200882
申请日：2016-07-01
Applicant: Infineon Technologies Austria AG
Inventor： Matthew Mascioli , Mattia Oddicini , Herbert Zojer
CPC classification number: H02M3/158 , H02M1/36 , H02M2001/0025
Abstract: A method of regulating an output voltage of a buck converter during a startup period in which the buck converter is first enabled includes regulating the output voltage of the buck converter to a reference voltage under current-mode control during a first part of the startup period, and regulating the output voltage of the buck converter to the reference voltage under voltage-mode control during a second, later part of the startup period. The reference voltage ramps up from an initial voltage at the beginning of the startup period to a target voltage at the end of the startup period. Buck converter embodiments are also described.
-
公开(公告)号：US12072830B2
公开(公告)日：2024-08-27
申请号：US17527424
申请日：2021-11-16
Applicant: Infineon Technologies Austria AG
Inventor： David R. Lewis , Paul M. Gitahi , Suejong Choi Perranoski , Mattia Oddicini , Scott W. Southwell , Robert Reissfelder
CPC classification number: G06F13/4282 , G06F1/26 , G06F13/4022
Abstract: An apparatus includes processing hardware, storage hardware, and serial communication hardware. The processing hardware receives selection of a serial communication protocol. The serial communication protocol is selected amongst multiple serial communication protocols to control operation of a power converter. Via the processing hardware or other suitable entity, the storage hardware is populated with a set of command decode functions (a.k.a., command descriptors) assigned to the selected serial communication protocol. During operation, the serial communication hardware receives commands over a serial communication interface and executes the received commands via the set of command decode functions in the storage hardware. Each of the multiple commands communicated over the serial communication interface is encoded in accordance with the selected serial communication protocol. The serial communication hardware uses the set of command decode functions to execute the received commands.
-
公开(公告)号：US20230153263A1
公开(公告)日：2023-05-18
申请号：US17527424
申请日：2021-11-16
Applicant: Infineon Technologies Austria AG
Inventor： David R. Lewis , Paul M. Gitahi , Suejong Choi Perranoski , Mattia Oddicini , Scott W. Southwell , Robert Reissfelder
CPC classification number: G06F13/4282 , G06F13/4022 , G06F1/26
Abstract: An apparatus includes processing hardware, storage hardware, and serial communication hardware. The processing hardware receives selection of a serial communication protocol. The serial communication protocol is selected amongst multiple serial communication protocols to control operation of a power converter. Via the processing hardware or other suitable entity, the storage hardware is populated with a set of command decode functions (a.k.a., command descriptors) assigned to the selected serial communication protocol. During operation, the serial communication hardware receives commands over a serial communication interface and executes the received commands via the set of command decode functions in the storage hardware. Each of the multiple commands communicated over the serial communication interface is encoded in accordance with the selected serial communication protocol. The serial communication hardware uses the set of command decode functions to execute the received commands.
-
公开(公告)号：US20220131552A1
公开(公告)日：2022-04-28
申请号：US17077475
申请日：2020-10-22
Applicant: Infineon Technologies Austria AG
Inventor： Sujata Sen , Mattia Oddicini , Luca Petruzzi , Benjamim Tang
Abstract: A tracking analog-to-digital converter (ADC) for a power converter includes a first tracking loop and a second tracking loop. The first tracking loop is configured to track a voltage input to the tracking ADC using one or more comparators and has a re-clocking circuit to mitigate the impact of comparator output metastability, but introduces multi-cycle latency which increases a residual error of the voltage tracking provided by the first tracking loop. The second tracking loop is configured to supplement the voltage tracking provided by the first tracking loop and to reduce the residual error of the voltage tracking for dynamic changes at the voltage input. The second tracking loop has a single-cycle latency and is implemented with logic that is less sensitive to logic errors due to comparator metastability. Corresponding methods of voltage tracking and an electronic system are also described.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.037 seconds)
