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    Memory with separate read and write paths
    5.
    发明授权
    Memory with separate read and write paths 有权
    内存具有单独的读写路径

    公开(公告)号：US08400823B2

    公开(公告)日：2013-03-19

    申请号：US12774016

    申请日：2010-05-05

    申请人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    发明人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    IPC分类号： G11C11/00

    CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

    摘要翻译： 存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。 巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。 磁性隧道结数据单元电耦合在读取位线和读取源极线之间。 磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。 写入电流通过巨磁电阻单元，以将巨磁阻单元切换到高电阻状态和低电阻状态之间。 磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

    MRAM DIODE ARRAY AND ACCESS METHOD
    6.
    发明申请
    MRAM DIODE ARRAY AND ACCESS METHOD 有权
    MRAM二极管阵列和访问方法

    公开(公告)号：US20130003448A1

    公开(公告)日：2013-01-03

    申请号：US13611225

    申请日：2012-09-12

    申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1675 ,  G11C11/1659

    摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

    摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

    MRAM diode array and access method
    7.
    发明授权
    MRAM diode array and access method 有权
    MRAM二极管阵列和访问方式

    公开(公告)号：US08289746B2

    公开(公告)日：2012-10-16

    申请号：US12948824

    申请日：2010-11-18

    申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    IPC分类号： G11C5/08 ,  G11C27/00 ,  G11C11/00

    CPC分类号： G11C11/1675 ,  G11C11/1659

    摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

    摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

    MEMORY WITH SEPARATE READ AND WRITE PATHS
    8.
    发明申请
    MEMORY WITH SEPARATE READ AND WRITE PATHS 有权
    具有单独读取和写入数据的存储器

    公开(公告)号：US20110090733A1

    公开(公告)日：2011-04-21

    申请号：US12974679

    申请日：2010-12-21

    申请人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    发明人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    IPC分类号： G11C11/15

    CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

    摘要翻译： 存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。 巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。 磁性隧道结数据单元电耦合在读取位线和读取源极线之间。 磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。 写入电流通过巨磁电阻单元，以在高电阻状态和低电阻状态之间切换巨磁电阻单元。 磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

    Memory with separate read and write paths
    9.
    发明授权
    Memory with separate read and write paths 有权
    内存具有单独的读写路径

    公开(公告)号：US07881098B2

    公开(公告)日：2011-02-01

    申请号：US12198416

    申请日：2008-08-26

    申请人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    发明人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    IPC分类号： G11C11/00

    CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.

    摘要翻译： 存储单元包括电耦合在写位线和写入源线之间的电磁耦合单元和电耦合在读取位线和读取源极线之间的磁性隧道结数据单元的巨磁电阻单元。 通过巨磁电阻单元的写入电流将巨磁阻单元切换到高电阻状态和低电阻状态之间。 磁隧道结数据单元被配置为通过与巨磁阻单元的静磁耦合在高电阻状态和低电阻状态之间切换。 磁隧道结数据单元由通过磁性隧道结数据单元的读取电流读取。

    MRAM diode array and access method
    10.
    发明授权
    MRAM diode array and access method 有权
    MRAM二极管阵列和访问方式

    公开(公告)号：US08514605B2

    公开(公告)日：2013-08-20

    申请号：US13611225

    申请日：2012-09-12

    申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    IPC分类号： G11C5/08 ,  G11C27/00 ,  G11C11/00

    CPC分类号： G11C11/1675 ,  G11C11/1659

    摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

    摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。