公开(公告)号：US11869872B2

公开(公告)日：2024-01-09

申请号：US17634081

申请日：2021-08-05

Applicant: Institute of Semiconductors, Guangdong Academy of Sciences

Inventor： Yao Wang ,  Yunzhi Ling ,  Yinhua Cui ,  Chuan Hu ,  Zibai Li ,  Wei Zhao ,  Zhitao Chen

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08113 ,  H01L2224/08146 ,  H01L2224/80896 ,  H01L2924/15153

Abstract: A chip stack packaging structure and method includes: a base chip layer, including a base chip with pins on the front surface; at least one stacked chip layer, which is formed on the base chip layer, has an inter-chip insulating layer and at least one stacked chip attached to the insulating layer and pins on the front surface, where the front surface of the stacked chip faces the front surface of the base chip; and a top insulating layer, stacked on the stacked chip layer farthest from the base chip layer. A vertical interconnection hole is formed inside the inter-chip insulating layer to allow the corresponding pins to be communicated vertically so as to be electrically connected. Inside the vertical interconnection hole, a conductive material layer is formed that makes the corresponding pins electrically connected; the stacked chip is thinned and reduced after being attached to the inter-chip insulating layer.

公开(公告)号：US11609672B1

公开(公告)日：2023-03-21

申请号：US17654524

申请日：2022-03-11

Applicant: Institute of Semiconductors, Guangdong Academy of Sciences

Inventor： Zibai Li ,  Yao Wang ,  Chuan Hu ,  Boqian Chen ,  Zhitao Chen

IPC: G06F3/044 ,  G06F3/041

Abstract: A touch control substrate, a preparation method thereof, a touch control module, and a display device are provided. The touch control substrate comprises: a substrate, a conductive functional layer, and a second protection medium. The conductive functional layer is arranged on one side of the substrate, and comprises patterned nano conductive structure, first protection medium, and frame lead structure. The conductive functional layer is protected by providing a two-layer protection medium structure, wherein the first protection medium fixes the structural position of the nano conductive layer and protects the partial structure of the conductive functional layer, and the second protection medium at least completely covers the nano conductive layer located in the conductive functional area; and at the same time, the touch control substrate directly disposes the frame lead layer in the peripheral area of the nano conductive layer, making the frame lead directly contacting the nano conductive layer.

公开(公告)号：US20230178514A1

公开(公告)日：2023-06-08

申请号：US17634081

申请日：2021-08-05

Applicant: Institute of Semiconductors, Guangdong Academy of Sciences

Inventor： Yao Wang ,  Yunzhi Ling ,  Yinhua Cui ,  Chuan Hu ,  Zibai Li ,  Wei Zhao ,  Zhitao Chen

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/0652 ,  H01L23/49827 ,  H01L24/08 ,  H01L25/50 ,  H01L24/80 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L2224/80896 ,  H01L2224/08113 ,  H01L2224/08146 ,  H01L2924/15153

Abstract: A chip stack packaging structure and method includes: a base chip layer, including a base chip with pins on the front surface; at least one stacked chip layer, which is formed on the base chip layer, has an inter-chip insulating layer and at least one stacked chip attached to the insulating layer and pins on the front surface, where the front surface of the stacked chip faces the front surface of the base chip; and a top insulating layer, stacked on the stacked chip layer farthest from the base chip layer. A vertical interconnection hole is formed inside the inter-chip insulating layer to allow the corresponding pins to be communicated vertically so as to be electrically connected. Inside the vertical interconnection hole, a conductive material layer is formed that makes the corresponding pins electrically connected; the stacked chip is thinned and reduced after being attached to the inter-chip insulating layer.

公开(公告)号：US12112956B2

公开(公告)日：2024-10-08

申请号：US17434480

申请日：2021-02-08

Applicant: Institute of Semiconductors, Guangdong Academy of Sciences

Inventor： Yao Wang ,  Zibai Li ,  Yunzhi Ling ,  Xun Xiang ,  Yinhua Cui ,  Chuan Hu ,  Zhitao Chen

IPC: H01L21/48 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L21/485 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L25/0655 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/211 ,  H01L2924/381

Abstract: Provided are a chip interconnection package structure and method, including: forming a sacrificial pattern layer on a support structure; forming an interconnection winding pattern layer on the sacrificial pattern layer, wherein the interconnection winding pattern layer is corresponding to a sacrificial pattern of the sacrificial pattern layer in position; forming a first insulating layer on the interconnection winding pattern layer; forming a plurality of chips arranged at intervals on the first insulating layer, wherein the plurality of chips are respectively corresponding to the interconnection winding pattern of the interconnection winding pattern layer in position; and removing the support structure, and forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, and making the first interconnection hole aligned and communicated with a first interconnection pin of the chip corresponding in projection position.