公开(公告)号：US09954541B1

公开(公告)日：2018-04-24

申请号：US15084067

申请日：2016-03-29

Applicant: Integrated Device Technology, Inc.

Inventor： Pankaj Goyal ,  Stephen E. Aycock

IPC: H03L7/183 ,  H03L7/099 ,  H03L7/093 ,  H03B5/36 ,  H03B5/32 ,  H03B5/12 ,  H03L7/23

CPC classification number: H03L7/183 ,  H03B5/12 ,  H03B5/32 ,  H03B5/326 ,  H03B5/366 ,  H03L7/099 ,  H03L7/23

Abstract: A frequency synthesizer comprising a first phase locked loop (PLL) circuit coupled to receive a reference frequency signal from a reference oscillator, the first PLL circuit comprising a first voltage controlled oscillator (VCO) having a bulk acoustic wave (BAW) resonator and a first fractional feedback divider circuit, the first PLL circuit outputting a first tuned frequency signal and a first plurality of integer divider circuits coupled to receive the first tuned frequency signal from the first PLL circuit and each of the first plurality of integer-only post-PLL divider circuits to provide one of a plurality of output frequency signals of the frequency synthesizer.

公开(公告)号：US09362928B1

公开(公告)日：2016-06-07

申请号：US14794782

申请日：2015-07-08

Applicant: Integrated Device Technology, Inc.

Inventor： Pankaj Goyal ,  Jagdeep Bal

IPC: H03L7/06 ,  H03L7/197 ,  H03L7/099 ,  H03L7/093

CPC classification number: H03L7/081 ,  H03L7/0814 ,  H03L7/1976

Abstract: A fractional N-frequency divider having a reduced fractional spurious output signal, which utilizes a multi-modulus frequency divider and an accumulator to generate a calibration-timing window that is used to calibrate two oscillator circuits and a phase compensation circuit. The calibrated phase compensation circuit is then used to mitigate the fractional spurs in the output signal of the fractional N-frequency divider. The fractional N-frequency divider may be implemented into a fractional N-frequency synthesizer.

Abstract translation: 具有减小的分数杂散输出信号的分数N分频器，其使用多模式分频器和累加器来产生用于校准两个振荡器电路和相位补偿电路的校准时序窗口。 然后使用校准的相位补偿电路来减轻分数N分频器的输出信号中的分数杂散。 分数N分频器可以被实现为分数N频率合成器。

公开(公告)号：US09581973B1

公开(公告)日：2017-02-28

申请号：US15083831

申请日：2016-03-29

Applicant: Integrated Device Technology, Inc.

Inventor： Pankaj Goyal ,  Jagdeep Bal ,  Stephen E. Aycock

IPC: G04F5/04 ,  H03B5/32 ,  H03K5/15

CPC classification number: G04F5/04 ,  G04G3/02 ,  H03B5/32 ,  H03B5/364 ,  H03B2200/0082 ,  H03K5/15006

Abstract: An integrated circuit comprising, a resonator, a first clock circuit for generating a first clock signal having a first frequency in response to the resonator, a second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by the programmable frequency divider and a clock mode control circuit coupled to the first clock circuit and the second clock circuit, the clock mode control circuit for gradually switching the resonator between the first oscillator circuit and the second oscillator circuit of the integrated circuit, using a shift register based state machine and utilizing the inertia of the resonator to smoothly transition between the two oscillators, to provide a dual mode clock output signal.

Abstract translation: 一种集成电路，包括谐振器，用于响应谐振器产生具有第一频率的第一时钟信号的第一时钟电路，用于响应谐振器产生具有第二频率的第二时钟信号的第二时钟电路，其中， 第二时钟信号的第二频率由可编程分频器和耦合到第一时钟电路和第二时钟电路的时钟模式控制电路确定，时钟模式控制电路用于在第一振荡器电路和第二时钟电路之间逐渐切换谐振器 振荡器电路，使用基于移位寄存器的状态机并利用谐振器的惯性在两个振荡器之间平滑地转换，以提供双模式时钟输出信号。