公开(公告)号：US20170330761A1

公开(公告)日：2017-11-16

申请号：US15528736

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jasmeet S. CHAWLA ,  Ruth A. BRAIN ,  Richard E. SCHENKER ,  Kanwal Jit SINGH ,  Alan M. MEYERS

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/48 ,  H01L23/522

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/485 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2224/16225

Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.