公开(公告)号：US20180069692A1

公开(公告)日：2018-03-08

申请号：US15255564

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  Ying ZHOU ,  John V. LOVELACE ,  Alberto David PEREZ

IPC: H04L7/033 ,  H04L7/08 ,  H04L7/00

CPC classification number: H04L7/0041 ,  G11C7/00 ,  G11C29/023 ,  G11C29/028 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0331

Abstract: Embodiments are generally directed to signal phase optimization in memory interface training. An embodiment of an apparatus includes an interface for at least one signal; and interface training logic capable of automatically adjusting a phase relationship between the signal and a strobe or clock, including establishing a phase delay of the signal and a phase delay of the strobe or clock for training of the interface, wherein the interface training logic is capable of determining a phase delay reduction for the signal subsequent to measurement of an eye margin for the signal, the phase delay reduction to retain a sufficient delay to maintain the eye margin for sampling of the signal.