公开(公告)号：US20160372366A1

公开(公告)日：2016-12-22

申请号：US15254840

申请日：2016-09-01

Applicant: Intel Corporation

Inventor： Jun HE ,  Kevin J. FISCHER ,  Ying ZHOU ,  Peter K. MOON

IPC: H01L21/768 ,  H01L21/3205 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/0217 ,  H01L21/02252 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

公开(公告)号：US20150097292A1

公开(公告)日：2015-04-09

申请号：US14569342

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Jun HE ,  Kevin J. FISCHER ,  Ying ZHOU ,  Peter K. MOON

IPC: H01L23/532 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/0217 ,  H01L21/02252 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

Abstract translation: 制造用于微电子器件的封盖互连的方法，其包括封盖层和互连件之间的任何间隙的密封特征以及由其形成的结构。 密封特征改善了互连的封装，其基本上减少或防止导电材料从封盖互连件的电迁移和/或扩散。

公开(公告)号：US20180069692A1

公开(公告)日：2018-03-08

申请号：US15255564

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  Ying ZHOU ,  John V. LOVELACE ,  Alberto David PEREZ

IPC: H04L7/033 ,  H04L7/08 ,  H04L7/00

CPC classification number: H04L7/0041 ,  G11C7/00 ,  G11C29/023 ,  G11C29/028 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0331

Abstract: Embodiments are generally directed to signal phase optimization in memory interface training. An embodiment of an apparatus includes an interface for at least one signal; and interface training logic capable of automatically adjusting a phase relationship between the signal and a strobe or clock, including establishing a phase delay of the signal and a phase delay of the strobe or clock for training of the interface, wherein the interface training logic is capable of determining a phase delay reduction for the signal subsequent to measurement of an eye margin for the signal, the phase delay reduction to retain a sufficient delay to maintain the eye margin for sampling of the signal.