公开(公告)号：US09973356B1

公开(公告)日：2018-05-15

申请号：US15475690

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ram Livne ,  Ro'ee Eitan ,  Yoel Krupnik ,  Vladislav Tsirkin ,  Tomer Fael ,  Dror Lazar ,  Ariel Cohen ,  Alexander Pogrebinsky ,  Adee Ofir Ran

IPC: H03L7/08 ,  H04L25/03 ,  H03G3/20 ,  H04L25/06

CPC classification number: H04L25/03057

Abstract: One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.