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公开(公告)号:US09973356B1
公开(公告)日:2018-05-15
申请号:US15475690
申请日:2017-03-31
Applicant: Intel Corporation
Inventor: Ram Livne , Ro'ee Eitan , Yoel Krupnik , Vladislav Tsirkin , Tomer Fael , Dror Lazar , Ariel Cohen , Alexander Pogrebinsky , Adee Ofir Ran
CPC classification number: H04L25/03057
Abstract: One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.
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公开(公告)号:US20230198631A1
公开(公告)日:2023-06-22
申请号:US17556696
申请日:2021-12-20
Applicant: Intel Corporation
Inventor: Itamar Levin , Adee Ofir Ran
CPC classification number: H04B10/6971 , H04B10/6932 , H04B10/614 , H04B10/503
Abstract: Sampling circuitry for receiving an analog signal from photodetector circuitry and generating a sample analog signal. Equalization circuitry for generating an equalized signal comprising first and second sample values corresponding with a cursor tap and a first postcursor tap, and one or more third sample values corresponding with taps other than the cursor tap and the first postcursor tap. In the equalized signal, amplitudes of the first and second sample values are substantially equal while the third sample values are attenuated relative to the first and second sample values. The first and second sample values correspond with two or more first symbols of a first alphabet. Data slicer and modulo circuitry to generate a data signal based on the equalized signal and perform a modulo operation on the two or more first symbols and to generate one or more second symbols. The second symbols are according to a second alphabet.
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公开(公告)号:US11424901B2
公开(公告)日:2022-08-23
申请号:US16655834
申请日:2019-10-17
Applicant: Intel Corporation
Inventor: Adee Ofir Ran , Kent C. Lusted
IPC: H04L7/00
Abstract: Loop timing is performed in a Reconciliation Sublayer (RS) so that the transmit clock frequency can be adjusted to be equal to the receive clock frequency for the entire PHY (including the physical coding sublayer (PCS)). One of two partners is selected to be the timing Slave to the other. If only one partner is capable of loop timing, that partner becomes the Slave. If both partners are capable of loop timing, symmetry breaking can be used to determine which partner should become Slave.
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公开(公告)号:US11356306B2
公开(公告)日:2022-06-07
申请号:US15941071
申请日:2018-03-30
Applicant: Intel Corporation
Inventor: Nishantkumar Shah , Kevan A. Lillie , Adee Ofir Ran , Itamar Levin , Kent Lusted
Abstract: Technologies for cooperative link equalization include a network device with a network interface controller (NIC). The NIC is to monitor variation in a property of a link channel that connects the network device with a target network device. The NIC detects, based on the channel variation, an event that triggers a condition to change an equalization setting of the link channel. In response to the detection, the NIC communicates, via an in-band equalization control channel, changes to the equalization setting of the link channel to the target network device.
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公开(公告)号:US20200321978A1
公开(公告)日:2020-10-08
申请号:US16905200
申请日:2020-06-18
Applicant: Intel Corporation
Inventor: Adee Ofir Ran , Amir Mezer , Alon Meisler , Assaf Benhamou , Itamar Levin , Yoni Landau
Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.
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公开(公告)号:US10715357B2
公开(公告)日:2020-07-14
申请号:US16399802
申请日:2019-04-30
Applicant: Intel Corporation
Inventor: Adee Ofir Ran
Abstract: Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.
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公开(公告)号:US20190108111A1
公开(公告)日:2019-04-11
申请号:US15727326
申请日:2017-10-06
Applicant: Intel Corporation
Inventor: Itamar Fredi Levin , Tsion Vidal , Sagi Zalcman , Adee Ofir Ran
IPC: G06F11/277 , G06F11/22 , H03M13/15 , G06F13/42
Abstract: An apparatus to derive a symbol error rate of an interconnect under test from a detector error rate of the interconnect, including: an error storage buffer; an input interface to communicatively couple to a serializer-deserializer at a physical level of an interconnect and to receive an input bitstream via the PHY level of the interconnect; a bitstream regenerator; a synchronization interface to receive synchronization data for the bitstream regenerator to reconstruct a clean reference bitstream; and a comparator to: compare the input bitstream to the clean reference bitstream; identify an error in the input bitstream including identifying a difference between the clean reference bitstream and the input bitstream; and store an error record in the error storage buffer, the error record including the error prepended by a plurality of clean bits to enable an analyzer to locate the error within the input data stream and construct a DER therefrom.
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公开(公告)号:US20190044763A1
公开(公告)日:2019-02-07
申请号:US15941071
申请日:2018-03-30
Applicant: Intel Corporation
Inventor: Nishantkumar Shah , Kevan A. Lillie , Adee Ofir Ran , Itamar Levin , Kent Lusted
Abstract: Technologies for cooperative link equalization include a network device with a network interface controller (NIC). The NIC is to monitor variation in a property of a link channel that connects the network device with a target network device. The NIC detects, based on the channel variation, an event that triggers a condition to change an equalization setting of the link channel. In response to the detection, the NIC communicates, via an in-band equalization control channel, changes to the equalization setting of the link channel to the target network device.
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公开(公告)号:US11809353B2
公开(公告)日:2023-11-07
申请号:US15476936
申请日:2017-03-31
Applicant: INTEL CORPORATION
Inventor: Kevan A. Lillie , Shlomi Lalush , Yaakov Dalsace , Adee Ofir Ran , Assaf Benhamou , David Golodni , Itay Tamir , Amir Laufer
IPC: G06F13/20 , G06F13/38 , G06F13/16 , G06F9/4401 , G06F30/18
CPC classification number: G06F13/382 , G06F9/4411 , G06F13/16 , G06F13/20 , G06F30/18 , G06F2213/0024 , G06F2213/0026
Abstract: Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.
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公开(公告)号:US11240072B2
公开(公告)日:2022-02-01
申请号:US16894356
申请日:2020-06-05
Applicant: Intel Corporation
Inventor: Adee Ofir Ran
Abstract: Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.
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