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公开(公告)号:US11563107B2
公开(公告)日:2023-01-24
申请号:US16361881
申请日:2019-03-22
申请人: Intel Corporation
发明人: Chieh-Jen Ku , Bernhard Sell , Pei-Hua Wang , Nikhil Mehta , Shu Zhou , Jared Stoeger , Allen B. Gardiner , Akash Garg , Shem Ogadhoh , Vinaykumar Hadagali , Travis W. Lajoie
IPC分类号: H01L29/66 , H01L27/108 , H01L29/786
摘要: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).
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公开(公告)号:US20220208770A1
公开(公告)日:2022-06-30
申请号:US17696945
申请日:2022-03-17
申请人: Intel Corporation
发明人: Yih Wang , Abhishek A. Sharma , Tahir Ghani , Allen B. Gardiner , Travis W. Lajoie , Pei-hua Wang , Chieh-Jen Ku , Bernhard Sell , Juan G. Alzate-Vinasco , Blake C. Lin
IPC分类号: H01L27/108 , H01L23/522 , H01L23/528 , H01L27/06 , H01L27/12
摘要: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
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公开(公告)号:US11610894B2
公开(公告)日:2023-03-21
申请号:US16457657
申请日:2019-06-28
申请人: Intel Corporation
发明人: Travis W. Lajoie , Abhishek A. Sharma , Van H. Le , Chieh-Jen Ku , Pei-Hua Wang , Jack T. Kavalieros , Bernhard Sell , Tahir Ghani , Gregory George , Akash Garg , Julie Rollins , Allen B. Gardiner , Shem Ogadhoh , Juan G. Alzate Vinasco , Umut Arslan , Fatih Hamzaoglu , Nikhil Mehta , Yu-Wen Huang , Shu Zhou
IPC分类号: H01L27/108
摘要: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
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公开(公告)号:US20190326296A1
公开(公告)日:2019-10-24
申请号:US15956379
申请日:2018-04-18
申请人: Intel Corporation
发明人: Yih Wang , Abhishek A. Sharma , Tahir Ghani , Allen B. Gardiner , Travis W. Lajoie , Pei-hua Wang , Chieh-jen Ku , Bernhard Sell , Juan G. Alzate-Vinasco , Blake C. Lin
IPC分类号: H01L27/108 , H01L27/12 , H01L23/528 , H01L23/522 , H01L27/06
摘要: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
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公开(公告)号:US20190305081A1
公开(公告)日:2019-10-03
申请号:US15941557
申请日:2018-03-30
申请人: INTEL CORPORATION
发明人: Travis W. LaJoie , Abhishek A. Sharma , Juan Alzate-Vinasco , Chieh-Jen Ku , Shem O. Ogadhoh , Allen B. Gardiner , Blake C. Lin , Yih Wang , Pei-Hua Wang , Jack T. Kavalieros , Bernhard Sell , Tahir Ghani
IPC分类号: H01L29/06 , H01L27/12 , H01L21/764 , H01L21/02 , H01L29/423 , H01L27/105
摘要: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.
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公开(公告)号:US11329047B2
公开(公告)日:2022-05-10
申请号:US15956379
申请日:2018-04-18
申请人: Intel Corporation
发明人: Yih Wang , Abhishek A. Sharma , Tahir Ghani , Allen B. Gardiner , Travis W. Lajoie , Pei-hua Wang , Chieh-jen Ku , Bernhard Sell , Juan G. Alzate-Vinasco , Blake C. Lin
IPC分类号: H01L27/108 , H01L27/12 , H01L23/528 , H01L23/522 , H01L27/06
摘要: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
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