公开(公告)号：US11991873B2

公开(公告)日：2024-05-21

申请号：US18109780

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Yu-Wen Huang ,  Shu Zhou

IPC: H10B12/00

CPC classification number: H10B12/03 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US20230369501A1

公开(公告)日：2023-11-16

申请号：US17742631

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Cheng Tan ,  Yu-Wen Huang ,  Hui-Min Chuang ,  Xiaojun Weng ,  Nikhil J. Mehta ,  Allen B. Gardiner ,  Shu Zhou ,  Timothy Jen ,  Abhishek Anil Sharma ,  Van H. Le ,  Travis W. Lajoie ,  Bernhard Sell

IPC: H01L29/786 ,  H01L27/108

CPC classification number: H01L29/78606 ,  H01L27/10814 ,  H01L29/78696 ,  H01L27/10873

Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.

公开(公告)号：US11610894B2

公开(公告)日：2023-03-21

申请号：US16457657

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Yu-Wen Huang ,  Shu Zhou

IPC: H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US11832438B2

公开(公告)日：2023-11-28

申请号：US16457634

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Jared Stoeger ,  Yu-Wen Huang ,  Shu Zhou

IPC: H10B12/00 ,  H01L27/12 ,  H01L49/02

CPC classification number: H10B12/315 ,  H01L27/124 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/55 ,  H01L28/65 ,  H01L28/82 ,  H10B12/0335 ,  H10B12/312

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20230290722A1

公开(公告)日：2023-09-14

申请号：US17692350

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Juan Alzate Vinasco ,  Abhishek Anil Sharma ,  Van H. Le ,  Moshe Dolejsi ,  Yu-Wen Huang ,  Kimberly Pierce ,  Jared Stoeger ,  Shem Ogadhoh

IPC: H01L23/522 ,  H01L27/108 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L23/53266 ,  H01L23/53238 ,  H01L23/53223 ,  H01L23/5283

Abstract: An integrated circuit (IC) includes a first memory cell and a second memory cell. The first memory cell includes (i) a first transistor and (ii) a first capacitor coupled to the first transistor, where an upper electrode of the first capacitor is coupled to a first conductive structure. The second memory cell is above the first memory cell. The second memory cell includes (i) a second transistor and (ii) a second capacitor coupled to the second transistor. An upper electrode of the second capacitor is coupled to a second conductive structure. In an example, an interconnect feature includes a continuous and monolithic body of conductive material. In an example, the continuous and monolithic body extends through the second conductive structure, and further extends through the first conductive structure. In an example, the first and second memory cells are dynamic random access memory (DRAM) memory cells.