公开(公告)号：US11610894B2

公开(公告)日：2023-03-21

申请号：US16457657

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Yu-Wen Huang ,  Shu Zhou

IPC: H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US11832438B2

公开(公告)日：2023-11-28

申请号：US16457634

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Jared Stoeger ,  Yu-Wen Huang ,  Shu Zhou

IPC: H10B12/00 ,  H01L27/12 ,  H01L49/02

CPC classification number: H10B12/315 ,  H01L27/124 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/55 ,  H01L28/65 ,  H01L28/82 ,  H10B12/0335 ,  H10B12/312

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US11758711B2

公开(公告)日：2023-09-12

申请号：US17696945

申请日：2022-03-17

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-Hua Wang ,  Chieh-Jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H10B12/00 ,  H01L27/06 ,  H01L27/12

CPC classification number: H10B12/315 ,  H01L23/528 ,  H01L23/5223 ,  H01L23/5226 ,  H01L27/0605 ,  H01L27/124 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

公开(公告)号：US11563107B2

公开(公告)日：2023-01-24

申请号：US16361881

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Chieh-Jen Ku ,  Bernhard Sell ,  Pei-Hua Wang ,  Nikhil Mehta ,  Shu Zhou ,  Jared Stoeger ,  Allen B. Gardiner ,  Akash Garg ,  Shem Ogadhoh ,  Vinaykumar Hadagali ,  Travis W. Lajoie

IPC: H01L29/66 ,  H01L27/108 ,  H01L29/786

Abstract: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).

公开(公告)号：US11329047B2

公开(公告)日：2022-05-10

申请号：US15956379

申请日：2018-04-18

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-hua Wang ,  Chieh-jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L27/12 ,  H01L23/528 ,  H01L23/522 ,  H01L27/06

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

公开(公告)号：US12080643B2

公开(公告)日：2024-09-03

申请号：US16583691

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Juan G. Alzate Vinasco ,  Chieh-Jen Ku ,  Shem O. Ogadhoh ,  Allen B. Gardiner ,  Blake C. Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/5223 ,  H01L23/5226

Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

公开(公告)号：US11991873B2

公开(公告)日：2024-05-21

申请号：US18109780

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Yu-Wen Huang ,  Shu Zhou

IPC: H10B12/00

CPC classification number: H10B12/03 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US20190326296A1

公开(公告)日：2019-10-24

申请号：US15956379

申请日：2018-04-18

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-hua Wang ,  Chieh-jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L27/12 ,  H01L23/528 ,  H01L23/522 ,  H01L27/06

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

公开(公告)号：US20190305081A1

公开(公告)日：2019-10-03

申请号：US15941557

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Travis W. LaJoie ,  Abhishek A. Sharma ,  Juan Alzate-Vinasco ,  Chieh-Jen Ku ,  Shem O. Ogadhoh ,  Allen B. Gardiner ,  Blake C. Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L29/06 ,  H01L27/12 ,  H01L21/764 ,  H01L21/02 ,  H01L29/423 ,  H01L27/105

Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

公开(公告)号：US20230369501A1

公开(公告)日：2023-11-16

申请号：US17742631

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Cheng Tan ,  Yu-Wen Huang ,  Hui-Min Chuang ,  Xiaojun Weng ,  Nikhil J. Mehta ,  Allen B. Gardiner ,  Shu Zhou ,  Timothy Jen ,  Abhishek Anil Sharma ,  Van H. Le ,  Travis W. Lajoie ,  Bernhard Sell

IPC: H01L29/786 ,  H01L27/108

CPC classification number: H01L29/78606 ,  H01L27/10814 ,  H01L29/78696 ,  H01L27/10873

Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.