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公开(公告)号:US11610894B2
公开(公告)日:2023-03-21
申请号:US16457657
申请日:2019-06-28
申请人: Intel Corporation
发明人: Travis W. Lajoie , Abhishek A. Sharma , Van H. Le , Chieh-Jen Ku , Pei-Hua Wang , Jack T. Kavalieros , Bernhard Sell , Tahir Ghani , Gregory George , Akash Garg , Julie Rollins , Allen B. Gardiner , Shem Ogadhoh , Juan G. Alzate Vinasco , Umut Arslan , Fatih Hamzaoglu , Nikhil Mehta , Yu-Wen Huang , Shu Zhou
IPC分类号: H01L27/108
摘要: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.