公开(公告)号：US12230988B2

公开(公告)日：2025-02-18

申请号：US17383865

申请日：2021-07-23

Applicant: Intel Corporation

Inventor： Adrian Mocanu ,  Zeljko Zupanc ,  Derrick Wilson ,  Andrew Morning-Smith

IPC: G11C5/14 ,  G11C5/10 ,  H02J7/00 ,  H02J7/34

Abstract: Systems, apparatuses and methods may provide for technology that applies a constant current to a capacitor, wherein the constant current causes a linear voltage increase in the capacitor, and determines a capacitance based on the constant current, a voltage change in the capacitor during the linear voltage increase, and a time change corresponding to the voltage change.

公开(公告)号：US09857859B2

公开(公告)日：2018-01-02

申请号：US14977305

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Andrew Morning-Smith ,  Kai-Uwe Schmidt ,  Adrian Mocanu ,  Mike M. Ngo

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/28 ,  G06F1/30 ,  G06F1/3287

Abstract: Examples include techniques to power down output power rails for a storage device. In some examples, energy discharged from output capacitors for output power rails and energy discharged from input capacitors may be used to facilitate power down of power rails for the storage device.

公开(公告)号：US20220004342A1

公开(公告)日：2022-01-06

申请号：US17481796

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Jorge Ulises Martinez Araiza ,  Michael Leslie Roy ,  Andrew Morning-Smith

IPC: G06F3/06

Abstract: An embodiment of an electronic apparatus may include a substrate and a controller coupled to the substrate, the controller including circuitry to control access to a NAND-based storage media that includes a plurality of NAND devices located on the substrate and organized into two or more physical clusters with each NAND device uniquely assigned to one of the two or more physical clusters, perform data access to a first physical cluster of the two or more physical clusters at a first bandwidth, and perform data access to a second physical cluster of the two or more physical clusters at a second bandwidth that is slower than the first bandwidth. Other embodiments are disclosed and claimed.

公开(公告)号：US10405420B2

公开(公告)日：2019-09-03

申请号：US16218344

申请日：2018-12-12

Applicant: INTEL CORPORATION

Inventor： Andrew Morning-Smith ,  Eugene Lim ,  Meng Zhai

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/18

Abstract: Embodiments include devices and method related to a foldable printed circuit board that may be used in SSD applications. One embodiment relates to a foldable printed circuit board comprising a first rigid portion, a second rigid portion, and a first flexible region coupling the first rigid portion to the second rigid portion. The foldable printed circuit board also includes a third rigid portion and a second flexible region coupling the second rigid portion to the third rigid portion, wherein the first rigid portion and the third rigid portion each have a width that is less than that of the second rigid portion. Other embodiments are described and claimed.

公开(公告)号：US20190205214A1

公开(公告)日：2019-07-04

申请号：US16294198

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Andrew Morning-Smith ,  Brian Mcfarlane ,  Emily P. Chung ,  William Glennan

IPC: G06F11/14 ,  G06F1/30 ,  G06F1/3206

CPC classification number: G06F11/1441 ,  G06F1/30 ,  G06F1/3206 ,  G06F11/1438

Abstract: An embodiment of a semiconductor apparatus for use with a persistent storage media may include technology to detect a power interruption event, and track an amount of off-time for a persistent storage media after the detected power interruption event. Other embodiments are disclosed and claimed.

公开(公告)号：US10860521B2

公开(公告)日：2020-12-08

申请号：US15395821

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Andrew Morning-Smith ,  Jawad B. Khan ,  Fred W. Nance, Jr. ,  Wing-Gong Lew

IPC: G06F13/42 ,  G06F13/40

Abstract: Apparatuses, systems, and methods having positionally aware communication between a controller and a plurality of solid state drives (SSD) over a multi-wire serial bus is described. An example electronic device includes a multi-wire serial bus, multiple SSD connectors coupled to the multi-wire serial bus, and a serial bus position address (BPos) line to uniquely identify the physical position of each SSD connector with a unique BPos identifier (ID). The device also includes a serial bus controller coupled to the multi-wire serial bus and further comprising circuitry configured to communicate with a specific SSD connector at a known physical position by associating the BPos ID of the specific SSD connector with the communication.

公开(公告)号：US09977478B1

公开(公告)日：2018-05-22

申请号：US15391037

申请日：2016-12-27

Applicant: INTEL CORPORATION

Inventor： Andrew Morning-Smith ,  Adrian Mocanu ,  Zeljko Zupanc

IPC: G11C5/14 ,  G06F13/00 ,  G06F1/30 ,  G06F1/28

CPC classification number: G06F1/30 ,  G06F1/28 ,  G11C5/148

Abstract: Provided is a memory device, comprising a non-volatile memory, an energy store coupled to the non-volatile memory, and a power management module configurable to power up the non-volatile memory and provide read access to the non-volatile memory, in response to the energy store being charged to at least a first predetermined level. Provided also is a computational device that includes the memory device. Provided also is a method in which an energy store coupled to a non-volatile memory of a memory device is charged to at least a first predetermined level. The non-volatile memory is powered up and read access is provided to the non-volatile memory, in response to charging the energy store to at least the first predetermined level.

公开(公告)号：US11175713B2

公开(公告)日：2021-11-16

申请号：US16047358

申请日：2018-07-27

Applicant: Intel Corporation

Inventor： Zeljko Zupanc ,  Andrew Morning-Smith ,  Mary Goodman ,  Alice Allen ,  Simon Ramage ,  Justin Elkow

IPC: G06F1/30 ,  H02J7/00 ,  G01R31/392 ,  H02J7/34 ,  G01R31/40

Abstract: A nonvolatile storage device includes a power management system with a power loss imminent (PLI) capacitor to provide backup energy in case system power is lost. The power management system includes a circuit with a charging path for the PLI capacitor that includes a series current-limiting circuit, and a diode coupled in parallel with the current-limiting circuit, the diode having a cathode coupled to the charging circuit and an anode to couple to the PLI capacitor.

公开(公告)号：US20210351595A1

公开(公告)日：2021-11-11

申请号：US17383865

申请日：2021-07-23

Applicant: Intel Corporation

Inventor： Adrian Mocanu ,  Zeljko Zupanc ,  Derrick Wilson ,  Andrew Morning-Smith

IPC: H02J7/00 ,  G11C5/14

Abstract: Systems, apparatuses and methods may provide for technology that applies a constant current to a capacitor, wherein the constant current causes a linear voltage increase in the capacitor, and determines a capacitance based on the constant current, a voltage change in the capacitor during the linear voltage increase, and a time change corresponding to the voltage change.

公开(公告)号：US10936049B2

公开(公告)日：2021-03-02

申请号：US16396557

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Adrian Mocanu ,  Andrew Morning-Smith ,  Zeljko Zupanc ,  Derrick Wilson

IPC: G06F3/06 ,  G06F1/3296 ,  G06F1/3234

Abstract: An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) semiconductor chip having logic circuitry to implement a PMIC/PMIC interface having a downstream signal line and an upstream signal line. The downstream signal line to communicate any of multiple states that a downstream PMIC semiconductor chip is to implement with one of multiple voltage levels, where, different ones of the multiple voltage levels correspond to different ones of the multiple states. The upstream signal line is to communicate whether or not the downstream PMIC semiconductor chip is ready to receive a next one of the multiple voltage levels.