Load reduced nonvolatile memory interface

    公开(公告)号:US11500795B2

    公开(公告)日:2022-11-15

    申请号:US16664535

    申请日:2019-10-25

    Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

Patent Agency Ranking