公开(公告)号：US20200273508A1

公开(公告)日：2020-08-27

申请号：US16283128

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Balaji SRINIVASAN ,  Sandeep K. GULIANI ,  DerChang KAU ,  Ashir G. SHAH

IPC: G11C8/10 ,  G06F3/06

Abstract: A memory decoder enables the selection of a conductor of a row or column of a crosspoint array memory. The decoder includes a circuit to apply a bias voltage to select or deselect the conductor. The conductor can be either a wordline or a bitline. The decoder also includes a select device to selectively provide both high voltage bias and low voltage bias to the circuit to enable the circuit to apply the bias voltage. Thus, a single end device provides either rail to the bias circuit.

公开(公告)号：US20160071553A1

公开(公告)日：2016-03-10

申请号：US14479020

申请日：2014-09-05

Applicant: Intel Corporation

Inventor： Nicolas L. IRIZARRY ,  Balaji SRINIVASAN

IPC: G11C5/14 ,  G11C16/30 ,  G11C13/00

CPC classification number: G11C5/147 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C16/30

Abstract: Embodiments of bus circuits and related techniques are disclosed herein. In some embodiments, a bus circuit may include: a source follower arrangement, including a first transistor and a second transistor, coupled between a supply voltage and an access line of a memory cell, wherein the first transistor and the second transistor each have a gate terminal and wherein the access line is a bit line or a word line; a capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to a reference voltage; and a switch coupled between the first terminal of the capacitor and a voltage regulator. Other embodiments may be disclosed and/or claimed.

Abstract translation: 总线电路和相关技术的实施例在此公开。 在一些实施例中，总线电路可以包括：源极跟随器布置，包括耦合在电源电压和存储器单元的存取线之间的第一晶体管和第二晶体管，其中第一晶体管和第二晶体管各自具有栅极 并且其中所述访问线是位线或字线; 电容器，其具有耦合到所述第一晶体管的栅极端子并具有耦合到参考电压的第二端子的第一端子; 以及耦合在电容器的第一端子和电压调节器之间的开关。 可以公开和/或要求保护其他实施例。