公开(公告)号：US20180286921A1

公开(公告)日：2018-10-04

申请号：US15474154

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Andrea REDAELLI ,  Innocenzo TORTORELLI ,  Fabio PELLIZZER ,  Agostino PIROVANO ,  DerChang KAU

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  G11C13/00

CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608

Abstract: Described herein are multi-deck memory devices with an inverted deck. For example, in one embodiment a memory device includes a first deck of memory cells including layers of material, including a layer of storage material and a layer of selector material, and a second deck of memory cells over the first deck of memory cells, the second deck comprising layers of material in an order opposite relative to the first deck. In one such embodiment, conductive bitlines located between the first and second decks are common to both decks. Inverting the second deck can enable operating the decks symmetrically despite accessing the decks with opposite polarity voltages.

公开(公告)号：US20200273508A1

公开(公告)日：2020-08-27

申请号：US16283128

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Balaji SRINIVASAN ,  Sandeep K. GULIANI ,  DerChang KAU ,  Ashir G. SHAH

IPC: G11C8/10 ,  G06F3/06

Abstract: A memory decoder enables the selection of a conductor of a row or column of a crosspoint array memory. The decoder includes a circuit to apply a bias voltage to select or deselect the conductor. The conductor can be either a wordline or a bitline. The decoder also includes a select device to selectively provide both high voltage bias and low voltage bias to the circuit to enable the circuit to apply the bias voltage. Thus, a single end device provides either rail to the bias circuit.