公开(公告)号：US20030205406A1

公开(公告)日：2003-11-06

申请号：US10419400

申请日：2003-04-21

申请人： Intel Corporation

发明人： Paul H. Wermer ,  Brian Kaiser

IPC分类号： H05K001/16

CPC分类号： H05K1/115 ,  H05K1/162 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2203/135

摘要： The present invention includes forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as organic polymers and organic polymer mixtures. The present invention also includes forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and an embedded capacitor to reduce loop inductance.

公开(公告)号：US20020105774A1

公开(公告)日：2002-08-08

申请号：US09733484

申请日：2000-12-08

申请人： Intel Corporation

发明人： Paul H. Wermer ,  Brian Kaiser

IPC分类号： H01G004/06

CPC分类号： H05K1/115 ,  H05K1/162 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2203/135

摘要： The present invention includes forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as organic polymers and organic polymer mixtures. The present invention also includes forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and an embedded capacitor to reduce loop inductance.

摘要翻译： 本发明包括使用电涂覆工艺在有机衬底中的通孔通孔结构的导电层之间形成薄的，共形的，高完整性的电介质涂层，以减少导电层之间的环路电感。 使用高介电常数材料如有机聚合物和有机聚合物混合物形成电介质涂层。 本发明还包括在基本平坦的基板材料和嵌入式电容器之间的导电层之间形成薄的电介质涂层，以减小环路电感。