公开(公告)号：US20040129452A1

公开(公告)日：2004-07-08

申请号：US10741065

申请日：2003-12-19

发明人： Norman Lee Owens

IPC分类号： H05K001/16

CPC分类号： H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/0052 ,  H05K3/0097 ,  H05K2201/09063 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49222 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

摘要： A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M are greater than or equal to 2 and the size of the N by M array is selected such that each of the plurality of BGA substrates (12) maintains a planarity variation less than approximately 0.15 mm (approximately 6 mils). The printed wiring board (11) has a thickness (26) sufficient to minimize planarity variation and to allow a manufacturer to use automated assembly equipment without having to use support pallets or trays.

公开(公告)号：US20040118599A1

公开(公告)日：2004-06-24

申请号：US10328326

申请日：2002-12-23

申请人： MOTOROLA, INC.

发明人： Marc Chason ,  Jan Danvir

IPC分类号： H05K001/16

CPC分类号： B81C1/00333 ,  H01L21/563 ,  H01L23/48 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L31/0203 ,  H01L33/62 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2224/05599

摘要： The invention provides a method for attaching a flip chip to a printed wiring board. A bumped opto-electronic or electromechanical flip chip is provided. An underfill material is applied to a first portion of the flip chip, wherein a second portion of the flip chip is free of the underfill material. The flip chip is positioned on a printed wiring board, and a bumped portion of the flip chip is heated to electrically connect the flip chip to the printed wiring board. The second portion of the flip chip remains free of the underfill material when the flip chip is electrically connected to the printed wiring board.

摘要翻译： 本发明提供了一种将倒装芯片附接到印刷电路板的方法。 提供了一种凸起的光电或机电倒装芯片。 将底部填充材料施加到倒装芯片的第一部分，其中倒装芯片的第二部分没有底部填充材料。 倒装芯片位于印刷线路板上，并且加热倒装芯片的凸起部分以将倒装芯片电连接到印刷线路板。 当倒装芯片电连接到印刷线路板时，倒装芯片的第二部分保持没有底部填充材料。

公开(公告)号：US20040080922A1

公开(公告)日：2004-04-29

申请号：US10689457

申请日：2003-10-20

申请人： Alps Electric Co., Ltd.

发明人： Toru Aoyagi

IPC分类号： H05K001/16

CPC分类号： H01F17/0013 ,  H01F2017/0026 ,  H03H7/0115 ,  H03H2001/0085

摘要： A multilayered circuit board according to the present invention includes at least first and second stacked insulating layers. The first insulating layer has thereon a first electric conductor made of a conductive film constituting an inductor and a first electrode made of a conductive film constituting a capacitor. The second insulating layer has thereon a second electrode made of a conductive film constituting a capacitor. The first and second insulating layers are stacked such that the first and second electrodes are opposed to each other through the insulating layers. Therefore this provides a circuit board having a capacitor and an inductor through the use of the two insulating layers, thus providing an inexpensive thin circuit board with small parts count and high work-efficiency compared with the use of three insulating layers in a related art.

摘要翻译： 根据本发明的多层电路板至少包括第一和第二堆叠绝缘层。 第一绝缘层上具有由构成电感器的导电膜构成的第一导电体和由构成电容器的导电膜构成的第一电极。 第二绝缘层具有由构成电容器的导电膜构成的第二电极。 第一和第二绝缘层被堆叠成使得第一和第二电极通过绝缘层彼此相对。 因此，通过使用两个绝缘层，提供了具有电容器和电感器的电路板，因此相对于现有技术中使用三个绝缘层而言，提供了具有小零件数量和高工作效率的便宜的薄电路板。

公开(公告)号：US20040056298A1

公开(公告)日：2004-03-25

申请号：US10631773

申请日：2003-08-01

发明人： Brent S. Stone

IPC分类号： H01R024/00 ,  H05K001/16

CPC分类号： H01L23/49827 ,  H01L23/49805 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K7/1076 ,  H01L2924/00

摘要： A chip interface assembly and method of assembling a chip interface provide enhanced performance. The chip interface assembly includes a semiconductor package and a socket. The semiconductor package has a female contact architecture, where the female contact architecture is mated with a male contact architecture of the socket. By reversing the traditional male/female arrangement of conventional interconnection interfaces, difficulties associated with signaling throughput, clearance, hardware complexity and electrical losses can be obviated.

公开(公告)号：US20040045738A1

公开(公告)日：2004-03-11

申请号：US10250871

申请日：2003-07-09

发明人： Toshio Sugawa ,  Yoshihisa Takase

IPC分类号： H05K001/16

CPC分类号： H05K3/108 ,  H05K3/062 ,  H05K3/384 ,  H05K3/4069 ,  H05K3/4614 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/072 ,  H05K2203/1461 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156

摘要： The present invention provides a circuit board in which peeling strength is prevented from decreasing and connection resistance to conductive material is prevented from increasing, though the contact area decreases when the circuit board has a copper foil. This circuit board has metal film (105) for covering a through hole on at least one surface of insulating substrate (101) having the through hole filled with conductive material (104). Uneven layer (1069 with a thickness of 5 nullm or more is formed on a surface of metal film (105), and a metal layer is formed on the opposite surface to uneven layer (106).

摘要翻译： 本发明提供了一种电路板，其中防止剥离强度降低，并且当电路板具有铜箔时接触面积减小时，防止与导电材料的连接阻力增加。 该电路板具有金属膜（105），用于覆盖绝缘基板（101）的具有填充有导电材料（104）的通孔的至少一个表面上的通孔。 在金属膜（105）的表面上形成厚度为5μm以上的不均匀层（1069），在与凹凸层（106）相反的面上形成金属层。

公开(公告)号：US20030205406A1

公开(公告)日：2003-11-06

申请号：US10419400

申请日：2003-04-21

申请人： Intel Corporation

发明人： Paul H. Wermer ,  Brian Kaiser

IPC分类号： H05K001/16

CPC分类号： H05K1/115 ,  H05K1/162 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2203/135

摘要： The present invention includes forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as organic polymers and organic polymer mixtures. The present invention also includes forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and an embedded capacitor to reduce loop inductance.

公开(公告)号：US20030201122A1

公开(公告)日：2003-10-30

申请号：US10064061

申请日：2002-06-06

发明人： Chi-Hsing Hsu ,  Jimmy Hsu

IPC分类号： H05K001/16

CPC分类号： H01L23/49838 ,  H01L23/50 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H05K1/0219 ,  H05K3/3436

摘要： A flip-chip package substrate comprising a plurality of wiring layers, at least one insulation layers and at least one conductive plugs. The wiring layers are sequentially stacked such that an insulation layer is always sandwiched between two neighboring wiring layers. The conductive plug passes through the insulation layer for connecting with wiring layers. The uppermost wiring layer has a plurality of bump pads while the bottommost wiring layer has a plurality of ball pads. The bump pads on the uppermost wiring layer are organized into bump pad rings. Similarly, the ball pads on the bottommost wiring layer are organized into ball pad rings. Relative position of both the bump pad rings and the ball pad rings are organized according to functions in sequential order so that the wiring distance from the bump pads down to the ball pads is optimized.

摘要翻译： 一种倒装芯片封装基板，包括多个布线层，至少一个绝缘层和至少一个导电塞。 布线层依次层叠，绝缘层总是夹在两个相邻布线层之间。 导电插塞穿过绝缘层，用于与布线层连接。 最上面的布线层具有多个凸点焊盘，而最下面的布线层具有多个焊盘。 最上面的布线层上的凸点焊盘被组织成凸块垫环。 类似地，最下面布线层上的球垫被组织成球垫圈。 凸块垫环和球垫环的相对位置根据功能按顺序组织，从而优化了从凸块焊盘到球垫的接线距离。

公开(公告)号：US20030192176A1

公开(公告)日：2003-10-16

申请号：US10119963

申请日：2002-04-10

发明人： Benjamin N. Eldridge ,  Gaetan L. Mathieu

IPC分类号： H05K001/16 ,  H05K003/36 ,  G01R001/00 ,  H05K007/06

CPC分类号： B81C1/00214 ,  B81B7/04 ,  B81C3/002 ,  B81C2203/051 ,  G01R1/06711 ,  G01R1/06744 ,  G01R1/07314 ,  G01R1/07342 ,  G01R3/00 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/15174 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49151 ,  Y10T29/49204 ,  H01L2924/00

摘要： Methods of fabricating an array of aligned microstructures on a substrate are disclosed. The microstructures may be spring contacts or other microelements. The methods disclosed include construction of an alignment substrate, alignment of die elements with the alignment substrate, and fixation of the aligned die elements to a backing substrate.

摘要翻译： 公开了在衬底上制造排列的微结构阵列的方法。 微结构可以是弹簧触点或其他微量元件。 所公开的方法包括对准基板的构造，模具元件与对准基板的对准以及将对准的模具元件固定到背衬基板上。

公开(公告)号：US20030183418A1

公开(公告)日：2003-10-02

申请号：US10457129

申请日：2003-06-09

发明人： Abram M. Castro ,  Bernardo Gallegos ,  Gary Lee Engvall

IPC分类号： H01L023/34 ,  H01L023/42 ,  H05K001/16

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15173 ,  H05K1/113 ,  H05K3/205 ,  H05K3/4069 ,  H05K3/462 ,  H05K3/4658 ,  H05K3/4682 ,  H05K2201/096 ,  H05K2203/0191 ,  H05K2203/061 ,  H05K2203/066 ,  H01L2924/00

摘要： A circuit board according to the invention is made from two or more laminates each made of a fusible dielectric material, which laminates are bonded to each other along respective inner faces thereof. Each such laminate is preferably a pre-preg sheet containing both a heat-fusible resin and a reinforcing fiber filler to provide the desired stiffness and strength. A number of first electrical contacts are exposed on an outer face of the first laminate, and second electrical contacts are exposed on an outer face of the second laminate. The circuit board further includes a plurality of electrical conductors each running from a first contact to a second contact, the conductors including elongated conductive lines extending along one of the first or second laminates, and vias extending through the first and second laminates which have been filled with an electrically conductive via filler.

公开(公告)号：US20030179557A1

公开(公告)日：2003-09-25

申请号：US10183574

申请日：2002-06-27

发明人： N. Edward Berg

IPC分类号： H01L021/44 ,  H05K001/16

CPC分类号： H05K3/061 ,  H05K1/0266 ,  H05K3/0079 ,  H05K3/108 ,  H05K3/1275 ,  H05K2203/0113 ,  H05K2203/013 ,  H05K2203/0517 ,  H05K2203/0534 ,  H05K2203/0783 ,  H05K2203/105 ,  H05K2203/1173 ,  H05K2203/1545 ,  H05K2203/1572 ,  H05K2203/163

摘要： A method for producing printed circuits utilizing direct printing methods to apply a pattern mask to a substrate. The direct printing methods include correcting positional errors in a printing apparatus by ascertaining the errors in the printer through comparison of a printed pattern and a known standard pattern. Printer inputs are manipulated to compensate for the ascertained errors of the printer. The pattern mask applied by the corrected printer may be an etch resist mask for forming conductive pathways by an etching process, or the pattern mask may be a plating mask with conductive pathways being formed by a plating operation. The process of the present invention is applicable to forming both single-sided and double-sided printed circuit boards.

摘要翻译： 一种使用直接印刷方法制造印刷电路的方法，用于将图案掩模施加到基板上。 直接打印方法包括通过比较打印图案和已知标准图案来确定打印机中的错误来校正打印装置中的位置错误。 操作打印机输入以补偿确定的打印机错误。 由校正的打印机施加的图案掩模可以是用于通过蚀刻工艺形成导电通路的抗蚀剂掩模，或者图案掩模可以是具有通过电镀操作形成的导电路径的电镀掩模。 本发明的方法可用于形成单面和双面印刷电路板。