公开(公告)号：US20200233819A1

公开(公告)日：2020-07-23

申请号：US16833322

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Byoungchan OH ,  Sai Dheeraj POLAGANI ,  Joshua B. FRYMAN

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/0879 ,  G11C11/4093 ,  G11C5/04 ,  G11C29/42

Abstract: An apparatus is described. The apparatus includes a rank of memory chips to couple to a memory channel. The memory channel is characterized as having eight transfers of eight bits of raw data per burst access. The rank of memory chips has first, second and third X4 memory chips. The X4 memory chips conform to a JEDEC dual data rate (DDR) memory interface specification. The first and second X4 memory chips are to couple to an eight bit raw data portion of the memory channel's data bus. The third X4 memory chip to couple to an error correction coding (ECC) information portion of the memory channel's data bus.

公开(公告)号：US20210019225A1

公开(公告)日：2021-01-21

申请号：US17031772

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Byoungchan OH ,  Wei WU

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/29

Abstract: Examples include techniques to improve implement an error correction codeword (ECC) scheme to protect data stored to a memory from both hard and random bit errors using a hybrid ECC scheme that includes generation of first and second codewords to protect the data.