公开(公告)号：US10164660B1

公开(公告)日：2018-12-25

申请号：US15390352

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Simon Finn ,  Martin Langhammer ,  Sami Mumtaz

IPC: G11C29/00 ,  H03M13/15 ,  G06F11/10 ,  G11C29/52 ,  H03M13/00

Abstract: An integrated circuit may include a Reed-Solomon decoder that receives a transmitted code word and an associated bit mask and that generates a corresponding corrected message. The bit mask indicates an erasure pattern for the received code word. The Reed-Solomon decoder may include a syndrome generator, a multiplication circuit, a read-only memory (ROM) circuit, an address compressor, and an aggregation circuit. The syndrome generator may receive the transmitted code word and generate a corresponding syndrome. The address compressor may receive the bit mask and generate a corresponding unique address for accessing the ROM circuit. The ROM circuit may then output an inverse parity matrix based on the unique address. The multiplication circuit may multiply the syndrome by the retrieved inverse parity matrix to output corrected symbols. The aggregation circuit may then path the received code word with the corrected symbols to obtain the corrected message.

公开(公告)号：US10074409B2

公开(公告)日：2018-09-11

申请号：US15421090

申请日：2017-01-31

Applicant: Intel Corporation

Inventor： Simon Finn ,  Carl Ebeling

IPC: G11C7/10 ,  G11C8/00

CPC classification number: G11C7/1012 ,  G06F5/06 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/20 ,  G11C8/00 ,  G11C19/28

Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, and arithmetic and control circuitry. The arithmetic and control circuitry may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement simple first-in first-out modules and shift registers in addition to implementing memory modules with random access. Arithmetic and control circuitry may include a multiplexer that determines whether the configurable storage block is implementing simple first-in first-out modules or shift registers. When the configurable storage block implements first-in first-out modules, an up-down counter may be activated to generate a count value received at the multiplexer.

公开(公告)号：US10218386B1

公开(公告)日：2019-02-26

申请号：US15359548

申请日：2016-11-22

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Simon Finn ,  Sami Mumtaz

IPC: H03M13/00 ,  H03M13/15

Abstract: A Reed-Solomon encoder that supports multiple code words is provided. The encoder circuit may include partial syndrome calculation circuitry, three matrix multiplication circuits, and two adder circuits. The partial syndrome calculation circuitry may receive a message and generate partial syndromes. The first matrix multiplication circuit may multiply a lower portion of the partial syndromes by a small Lagrange matrix to produce a small parity symbol vector. The second matrix multiplication circuit may multiply the small parity symbol vector by a Vandermonde matrix to produce a product vector. The first adder circuit may add the product vector to an upper portion of the partial syndromes to produce a sum vector. The third matrix multiplication circuit may multiply the sum vector by a large Lagrange matrix to produce a large product vector. The large product vector may be selectively combined with the small parity symbol vector to generate final parity check symbols.

公开(公告)号：US20180218760A1

公开(公告)日：2018-08-02

申请号：US15421090

申请日：2017-01-31

Applicant: Intel Corporation

Inventor： Simon Finn ,  Carl Ebeling

IPC: G11C7/10 ,  G11C8/00

CPC classification number: G06F5/06 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/20 ,  G11C19/28

Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, and arithmetic and control circuitry. The arithmetic and control circuitry may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement simple first-in first-out modules and shift registers in addition to implementing memory modules with random access. Arithmetic and control circuitry may include a multiplexer that determines whether the configurable storage block is implementing simple first-in first-out modules or shift registers. When the configurable storage block implements first-in first-out modules, an up-down counter may be activated to generate a count value received at the multiplexer.