公开(公告)号：US20250006630A1

公开(公告)日：2025-01-02

申请号：US18342130

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Thomas Wagner ,  Georg Seidemann ,  Michael Langenbuch ,  Mamatha Yakkegondi Virupakshappa ,  Jonathan Jensen ,  Roshini Sachithanandan ,  Philipp Riess

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the bonded conductive structures may form radio frequency passive devices, such as inductors or transformers.

公开(公告)号：US20230197598A1

公开(公告)日：2023-06-22

申请号：US17554004

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Georgios Panagopoulos ,  Richard Geiger ,  Peter Baumgartner ,  Harald Gossner ,  Uwe Hodel ,  Michael Langenbuch ,  Johannes Xaver Rauh ,  Alexander Bechtold ,  Richard Hudeczek ,  Carla Moran Guizan

IPC: H01L23/522 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0924

Abstract: IC devices including inductors or transformers formed based on BPRs are disclosed. An example IC device includes semiconductor structures of one or more transistors, an electrically conductive layer, a support structure comprising a semiconductor material, and an inductor. The inductor includes an electrical conductor constituted by a power rail buried in the support structure. The inductor also includes a magnetic core coupled to the electrical conductor. The magnetic core includes magnetic rails buried in the support structure, magnetic TSVs buried in the support structure, and a magnetic plate at the backside of the support structure. The magnetic core includes a magnetic material, such as Fe, NiFe, CoZrTa, etc. In some embodiments, the IC device includes another power rail that is buried in the support structure and constitutes another electrical conductor coupled to the magnetic core. The two power rails and magnetic core can constitute a transformer.

公开(公告)号：US20230197527A1

公开(公告)日：2023-06-22

申请号：US17554061

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Peter Baumgartner ,  Alexander Bechtold ,  Uwe Hodel ,  Richard Hudeczek ,  Walther Lutz ,  Carla Moran Guizan ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Roshini Sachithanandan

IPC: H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L21/823821 ,  H01L23/5286 ,  H01L23/535 ,  H01L23/5226 ,  H01L27/0924

Abstract: IC devices including semiconductor devices isolated by BSRs are disclosed. An example IC device includes a first and a second semiconductor devices, a support structure, and a BSR. The BSR defines boundaries of a first and second section in the support structure. At least a portion of the first semiconductor device is in the first section, and at least a portion of the second semiconductor device is in the second section. The first semiconductor device is isolated from the second semiconductor device by the BSR. Signals from the first semiconductor device would not be transmitted to the second semiconductor device through the support structure. The BSR may be connected to a TSV or be biased. The IC device may include additional BSRs to isolate the first and second semiconductor devices. An BSR may be a power rail used for delivering power.

公开(公告)号：US20250006668A1

公开(公告)日：2025-01-02

申请号：US18342112

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Michael Langenbuch ,  Mamatha Yakkegondi Virupakshappa ,  Jonathan Jensen ,  Roshini Sachithanandan ,  Philipp Riess

IPC: H01L23/66 ,  H01L23/528

Abstract: Waveguide structures are built into integrated circuit devices using standard processing steps for semiconductor device fabrication. A waveguide may include a base, a top, and two side walls. At least one of the walls (e.g., the base or the top) may be formed in a metal layer. The base or top may be patterned to provide a transition to a planar transmission line, such as a coplanar waveguide. The side walls may be formed using vias.

公开(公告)号：US20230252214A1

公开(公告)日：2023-08-10

申请号：US17666616

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Richard Hudeczek ,  Carla Moran Guizan ,  Peter Baumgartner ,  Richard Geiger ,  Alexander Bechtold ,  Uwe Hodel ,  Walther Lutz ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Roshini Sachithanandan

IPC: G06F30/392 ,  H01L27/02

CPC classification number: G06F30/392 ,  H01L27/0207

Abstract: Methods for providing fill patterns for IC devices are disclosed. An example method includes detecting a first device and a second device in an image, e.g., a two- or three-dimensional image representing the IC device. A line is defined based on the devices. The line divides the image into a first section and a second section. A first structure is generated based on the first device. A second structure is generated based on the second device. The second structure is a mirror image of the first structure across the line. A first fill pattern is generated in the first section based on the first structure. A second fill pattern is generated in the second section based on the first fill pattern, e.g., through a reflection transformation of the first fill pattern across the line. The two fill patterns represent patterns of fill structures to be included in the IC device.

公开(公告)号：US20240387353A1

公开(公告)日：2024-11-21

申请号：US18320763

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Michael Langenbuch ,  Carla Moran Guizan ,  Mamatha Yakkegondi Virupakshappa ,  Roshini Sachithanandan ,  Philipp Riess ,  Jonathan Jensen ,  Peter Baumgartner ,  Georg Seidemann

IPC: H01L23/522 ,  H01L23/66

Abstract: Methods and apparatus are disclosed for implementing capacitors in semiconductor devices. An example semiconductor die includes a first dielectric material disposed between a first metal interconnect and a second metal interconnect; and a capacitor positioned within a via extending through the first dielectric material between the first and second metal interconnects, the capacitor including a second dielectric material disposed in the via between the first and second metal interconnects.

公开(公告)号：US20230187313A1

公开(公告)日：2023-06-15

申请号：US17550335

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Richard Geiger ,  Alexander Bechtold ,  Uwe Hodel ,  Richard Hudeczek ,  Walther Lutz ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Roshini Sachithanandan

IPC: H01L23/48 ,  H01L23/66 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L23/66 ,  H01L23/5286 ,  H01L27/0886 ,  H01L2223/6616

Abstract: IC devices including transmission lines are disclosed. An example IC device includes two electrically conductive layers (first and second layers) and a support structure between the two electrically conductive layers. The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission is placed in the first layer. Conductors of the transmission line are placed in the second layer and are coupled to the first layer by TSVs. Another example IC device includes three electrically conductive layers (first, second, and third layers). The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission line is placed in the second layer and conductors of the transmission line are placed in the third layer. The conductors are coupled to the first layer by TSVs and coupled to the second layer by vias.