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公开(公告)号：US20160066724A1
公开(公告)日：2016-03-10
申请号：US14483023
申请日：2014-09-10
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Ruchir Saraswat , Richard J. Goldman , Chi Man Kan , Matthew T. Aitken , Colin L. Perry
CPC classification number: G01K13/00 , A47G21/02 , A47G2021/008 , A47G2200/186 , G01C19/00 , G01K2207/08 , G06Q30/016 , G06Q50/12
Abstract: Embodiments described herein relate generally to monitoring a dining session using smart smallwares. A smart smallware may sense usage or non-usage associated with a dining session of a customer. Based on the sensed non-usage of the smart smallware, the smart smallware may detect a period of inactivity. In response to the detected period of inactivity, the smart smallware may transmit an indication of the detected period of inactivity. This transmitted indication may cause an external monitoring device to notify a waitperson that a customer associated with that smart smallware may require attention. Other embodiments may be described and/or claimed.
Abstract translation: 本文所描述的实施例一般涉及使用智能小物件监视餐饮会话。 智能小型餐具可以感知与客户的餐饮会话相关联的使用或不使用。 基于感知到的智能小型软件的不使用，智能小型软件可以检测不活动的时间段。 响应于检测到的不活动时段，智能小型餐具可以发送检测到的不活动时段的指示。 该发送的指示可能导致外部监视设备通知等待人员，与该智能小型餐具相关联的客户可能需要注意。 可以描述和/或要求保护其他实施例。
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2.发明申请APPARATUSES, METHODS, AND SYSTEMS FOR JITTER EQUALIZATION AND PHASE ERROR DETECTION 审中-公开用于抖动均衡和相位错误检测的装置，方法和系统公开(公告)号：US20160241223A1
公开(公告)日：2016-08-18
申请号：US15019764
申请日：2016-02-09
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Chi Man Kan , Ruchir Saraswat
CPC classification number: H03K5/13 , H03D13/003 , H03K2005/00019 , H03L7/097 , H04B3/146 , H04L1/205
Abstract: Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.
Abstract translation: 实施例包括用于抖动均衡和相位误差检测的装置，方法和系统。 在实施例中，通信电路可以包括用于传递数据信号和时钟路径以传递时钟信号的数据路径。 抖动均衡器可以与数据路径和/或时钟路径耦合以分别向数据信号和/或时钟信号提供可编程延迟。 可以通过训练处理来确定延迟，其中可以通过调制频率来调制电源电压。 延迟可以取决于电源电压的值，例如电源电压的电压电平和/或抖动频率分量。 还描述了可以与通信电路和/或其他实施例一起使用的相位误差检测器。
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Patent Agency Ranking
公开(公告)号：US20160180679A1
公开(公告)日：2016-06-23
申请号：US14580727
申请日：2014-12-23
Applicant: INTEL CORPORATION
Inventor： Nicholas P. Cowley , Ruchir Saraswat , Colin L. Perry , Matthew T. Aitken , Richard J. Goldman , Chi Man Kan
Abstract: A method monitors the consumption of materials, including determining the presence of materials in a smart receptacle using a sensor located in the smart receptacle. A server is alerted when an actionable item is detected.
Abstract translation: 一种方法监测材料的消耗，包括使用位于智能插座中的传感器确定智能插座中材料的存在。 当检测到可操作的项目时，将提醒服务器。
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公开(公告)号：US09582977B2
公开(公告)日：2017-02-28
申请号：US14580727
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Ruchir Saraswat , Colin L. Perry , Matthew T. Aitken , Richard J. Goldman , Chi Man Kan
Abstract: A method monitors the consumption of materials, including determining the presence of materials in a smart receptacle using a sensor located in the smart receptacle. A server is alerted when an actionable item is detected.
Abstract translation: 一种方法监测材料的消耗，包括使用位于智能插座中的传感器确定智能插座中材料的存在。 当检测到可操作的项目时，将提醒服务器。
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5.发明授权Apparatuses, methods, and systems for jitter equalization and phase error detection 有权用于抖动均衡和相位误差检测的装置，方法和系统公开(公告)号：US09288019B2
公开(公告)日：2016-03-15
申请号：US14324062
申请日：2014-07-03
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Chi Man Kan , Ruchir Saraswat
CPC classification number: H03K5/13 , H03D13/003 , H03K2005/00019 , H03L7/097 , H04B3/146 , H04L1/205
Abstract: Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.
Abstract translation: 实施例包括用于抖动均衡和相位误差检测的装置，方法和系统。 在实施例中，通信电路可以包括用于传递数据信号和时钟路径以传递时钟信号的数据路径。 抖动均衡器可以与数据路径和/或时钟路径耦合以分别向数据信号和/或时钟信号提供可编程延迟。 可以通过训练处理来确定延迟，其中可以通过调制频率来调制电源电压。 延迟可以取决于电源电压的值，例如电源电压的电压电平和/或抖动频率分量。 还描述了可以与通信电路和/或其他实施例一起使用的相位误差检测器。
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公开(公告)号：US20160006544A1
公开(公告)日：2016-01-07
申请号：US14324062
申请日：2014-07-03
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Chi Man Kan , Ruchir Saraswat
CPC classification number: H03K5/13 , H03D13/003 , H03K2005/00019 , H03L7/097 , H04B3/146 , H04L1/205
Abstract: Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.
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公开(公告)号：US09735765B2
公开(公告)日：2017-08-15
申请号：US15019764
申请日：2016-02-09
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Chi Man Kan , Ruchir Saraswat
CPC classification number: H03K5/13 , H03D13/003 , H03K2005/00019 , H03L7/097 , H04B3/146 , H04L1/205
Abstract: Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.
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