公开(公告)号：US20200286804A1

公开(公告)日：2020-09-10

申请号：US16292218

申请日：2019-03-04

Applicant: Intel Corporation

Inventor： John FALLIN ,  Daniel J. RAGLAND ,  Jonathan P. DOUGLAS

IPC: H01L23/34 ,  G06F11/14 ,  G06F1/20 ,  H01L23/473

Abstract: Circuitry to apply heat to a die while the die junction temperature is below a minimum die junction temperature of an operating die junction temperature range for the die is provided. The circuitry to avoid a system boot failure when the die junction temperature is below the operating die junction temperature range of the die.

公开(公告)号：US20200051884A1

公开(公告)日：2020-02-13

申请号：US16059513

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Sameer SHEKHAR ,  Amit Kumar JAIN ,  Kaladhar RADHAKRISHNAN ,  Jonathan P. DOUGLAS ,  Chin Lee KUAN

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  G06F1/20

Abstract: Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.